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Adaptive artificial neural network for robust estimation of parameters of asynchronous state

Adaptive artificial neural network for robust estimation of ...

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international conference on Environment and Electrical Engineering (EEEIC)

作者： Pawel Kostyla Tomasz Sikorski Zbigniew Waclawek Bogdan Leszkiewicz Department of Electrical Engineering Wroclaw University of Technology Wroclaw Poland Department of Regional Economy and Tourism in Jelenia Gora Wroclaw University of Economics Wroclaw Poland

In many applications, very fast methods are required for estimating of amplitudes of current signals distorted by noise. In this paper new parallel algorithms are proposed, which can be implemented by analogue adaptive circuits employing selected neural networks principles. algorithms based on the total least-squares (TLS) and the robust total least-squares (RTLS) criteria are developed and used to detection of asynchronous state of synchronous machines. the problems are formulated as optimization tasks and solved using the steepest descent continuous-time optimization algorithm. the corresponding architectures of analogue neuron-like adaptive processors are also shown. the developed networks are more robust against noise in the measured signal than other known neural network algorithms. the network based on the TLS criterion realizes the optimization process under the assumption that the signal model can also be deteriorated (frequency or sampling interval fluctuation and so forth). the TLS estimation effect is better and more reliable than the corresponding LS structure, when higher sampling frequency and a wider sampling window is applied. An asynchronous state of a synchronous machine may be identified through determining the amplitudes of particular components of stator's current provided that a constant slip value is assumed. Following a synchronism loss, this adopted value is assumed to be achieved and, for sure, exceeded. this work provides a description of artificial neural networks realising mentioned task of asynchronous state detection. Extensive computer simulations confirm the validity and performance of the proposed algorithms.

关键词： Stators Noise Robustness Estimation Synchronous machines Optimization Signal processing algorithms

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A Reconfigurable Computing Approach for Efficient and Scalable parallel Graph Exploration

A Reconfigurable Computing Approach for Efficient and Scalab...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Brahim Betkaoui Yu Wang David B. thomas Wayne Luk Department of Computing Imperial College London London UK Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University Beijing China Department of Electrical and Electronic Engineering Imperial College London London UK

In many application domains, data are represented using large graphs involving millions of vertices and billions of edges. Graph exploration algorithms, such as breadth-first search (BFS), are largely dominated by memory latency and are challenging to process efficiently. In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems. Our methodology is based on a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of the hardware capabilities of both FPGAs and the parallel memory subsystem. To validate our methodology, we provide a detailed design description of the Breadth-First Search algorithm on an FPGA-based high performance computing system. Using graph data based on the power-law graphs found in real-word problems, we are able to achieve performance results that are superior to those of high performance multi-core systems in the recent literature for large graph instances, and a throughput in excess of 2.5 billion traversed edges per second on RMAT graphs with 16 million vertices and over a billion edges. Using four Virtex-5 LX330 FPGAs based on 65nm technology and running at 75MHz, our BFS design achieves more than twice the speed of a 32-core Xeon X7560 based on 45nm technology and running at 2.26GHz.

关键词： Hardware Algorithm design and analysis Random access memory Arrays Field programmable gate arrays Kernel

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Compute intensive in advanced wireless sensor node: Potential solution

Compute intensive in advanced wireless sensor node: Potentia...

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Mosharaka international conference on Communications, Computers and Applications, MIC-CCA

作者： Helmi Ahmed Mohamed Masmoudi METS Research Group-National Engineers School of Sfax Tunisia

ISBN: (纸本)9781467352307

For the past decade, there has been rapid development and advancement in the communication and sensor technologies that result in the growth of a new, attractive and challenging research area. In the other side, Wireless Sensor Network complexity applications have grown permanently, this rapid growth compared to the internal logical architecture of sensor node has increased the gap between sensor network and its applications. Sensor node always has preserved the same set of calculation logic regardless of application evolution. Developed applications such as video surveillance, intelligence, reconnaissance and applications emulating eyes found in robots are very hungry applications for intensive data and massive computing. Not only will it be necessary for nodes to process information, but they will have to react flexibly and act quickly when tasks become important. A fixed way of information processing is insufficient. there is no doubt that using a sophisticated solution to meet the critical needs of this type of application is very interesting to close the gap and will introduce a new challenge in the intensive data processing in sensor networks. In this paper we propose a novel architecture for intelligent sensor node based on multiprocessors engine enclosing a dedicated communication mechanism that's called network on-chip (NoC).

关键词： Wireless Sensor Network Node Intensive-information Intensive-compute Imote multiprocessors Network on Chip parallel compute Multiprocessor Line of nodes network-on-chip Wireless sensor networks Sensor networks Sensors

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Efficient parallel Process Migration Algorithm Using Statistical Approach 4th

Efficient Parallel Process Migration Algorithm Using Statist...

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international conference on Computational Intelligence and Communication Networks

作者： Chandu D. Vaidya M. B. Chandak M-Tech (4th SEM) Nagpur India

ISBN: (纸本)9781467329811

the cost or complexity of serial algorithms is estimated in terms of the space i.e. memory and time i.e. processor cycle. parallel algorithms need to optimize one or more resources and also the communication between different processors. parallel processing involves a technique by which complex data sets are broken into individual threads and processed simultaneously on one or more cores. If a system is doing one task which consists of large computation, it will take more time to finish that task. the proposed approach enables the efficient exploitation of parallelism by well-balanced distribution of workload to host processors and minimizes the overhead on single computer. Data division and migration is used for parallel processing. But if the process is migrated, it needs to take care of process for execution like pause, resume etc. It also needs to set check points for processes that become very complicated and time consuming. the proposed work divides the task into some subset on the basis of global decision and migrate that task among the slave computers. the output from the slave computers are collected on the master node. the proposed work considers the SIMD and MIMD computer applications for comparing the result for analysis. the proposed work contains static approach for process migration using data level parallelism. It creates small chunks of data from the large data set to reduce the execution time. It considers the memory availability of the slave nodes for taking the decision of data transfer. the proposed approach considers equal and unequal data division and distribution for load balancing. In addition to computational cost, the cost of memory accesses is an important factor for determining program performance. Proposed work is based on memory availability of slave nodes, as per their availability they are given an additional task to perform.

关键词： Component parallel processing Load balancing Cluster computing Process migration

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Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology

Development of a versatile low-power 24 GHz phased array fro...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： G. Tasselli B. Wang S. Ghamari C. Robert C. Botteron P.A. Farine Electronics and Signal Processing Laboratory École Polytechnique Fédérale de Lausanne Neuchatel Switzerland

this paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multiple parallel RF channels in the FE and complex algorithms for beam steering or high bit-rate demodulation in the digital part. In contrast, we target in this paper applications where both beam steering algorithms and data demodulation are relatively simple and hence achievable with low-power digital signal processing. More specifically, we report on four significant building blocks of the architecture, a Low Noise Amplifier (LNA), a Vector Modulator Phase Shifter (VMPS), a Quadrature Voltage Controlled Oscillator (QVCO) and an Analogue to Digital Converter (ADC) that have been designed the first three in 90nm and the last in 180nm CMOS technology. the LNA shows 24.4 dB gain, 3.4 dB NF and -24.4 dBm input P1dB. the single quadrant VMPS has more than 90° of phase control range and shows less than 0.7 dB of gain variation over phase shifting. the QVCO which consumes less than 32mW, buffer included, has a tuning range of 8%. the 6bit 20 MS/s ADC consumes 1.8mW.

关键词： Gain Transceivers Computer architecture CMOS integrated circuits Radar Microprocessors Sensors

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A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer 12

A Framework for exploration of parallel SystemC simulation o...

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Proceedings of the 5th international ICST conference on Simulation Tools and Techniques

作者： Christoph Roth Simon Reder Oliver Sander Michael Hübner Jürgen Becker Karlsruhe Institute of Technology (KIT) Karlsruhe Germany

ISBN: (纸本)9781450315104

Since the number of cores integrated on a single die is expected to increase steadily, new memory and communication architectures as well as programming methods are needed and currently explored by manufacturers. In this context, Intel Labs developed the Single-chip Cloud Computer (SCC), a 48-core experimental processor, serving as a platform for many-core software research. Within this paper a framework targeting the investigation of SystemC kernel parallelization on the SCC is presented. the framework provides the basis for implementation of different synchronization schemes while combining distributed and shared memory programming models and exploiting multiple distinct address spaces. As a case study, a synchronous parallelization scheme is preliminarily evaluated by means of several simulation models of different accuracy. Results of the analysis give a first evidence of the applicability of the synchronous parallelization method on the homogeneous non-cache coherent manycore architecture of the SCC for detailed system simulation.

关键词： single-chip cloud computer parallel simulation SystemC

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E-voting for Swiss abroad: A joint project between the confederation and the cantons

E-voting for Swiss abroad: A joint project between the confe...

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5th international conference on Electronic Voting, EVOTE 2012

作者： Driza-Maurer, Ardita Spycher, Oliver Taglioni, Geo Weber, Anina Federal Chancellery Section for Political Rights Bundeshaus West 3003 Bern Switzerland

ISBN: (纸本)9783885792994

the ever-increasing number of expatriates has fed the political debate on the voting rights of Swiss abroad over the last two decades. More than the right to vote itself, the effective exercise of voting rights has become a much-discussed issue. Swiss expatriates are able to vote at the federal level, which means they are invited to vote in popular votes and referendums up to four times a year and in elections every four years. they vote mainly by post and are faced with delays inherent to this method of voting and are sometimes disenfranchised as a result. Internet voting considerably accelerates the return of the ballot. Its introduction has been one of the main demands of Swiss living abroad. In parallel, the federal and cantonal authorities have planned to gradually and pragmatically adapt direct democracy instruments and voting methods to the digital environment in a prudent and long-term process. Internet voting was launched at the beginning of the 21st century and is one of the key projects of the Confederation's e-government strategy. three Internet voting systems have been developed so far by the cantons of Zurich, Neuchâtel, and Geneva. Internet voting was first offered to Swiss expats in June 2008. For the latest federal elections on February 13, 2011, some 55,000 Swiss abroad had the possibility to vote via Internet;on the federal elections on October 23, 2011, some 22,000 Swiss abroad registered in four cantons took part in the very first Internet voting trial during a federal election. Half of Swiss cantons have now introduced Internet voting, mainly for citizens abroad. While it is too early to draw conclusions on whether Internet voting fosters participation of expatriates in Swiss political life, recent experience clearly shows that Internet voting is well accepted. the success of the Swiss model of the introduction of evoting can be explained with the following elements: joint strategic planning (the roadmap), a good inter-cantonal cooperation with

关键词： Government data processing

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Data-intensive computing with map-reduce and hadoop

Data-intensive computing with map-reduce and hadoop

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international conference on Application of Information and Communication Technologies (AICT)

作者： Shamil Humbetov Department of Computer Engineering Qafqaz University Azerbaijan Azerbaijan

Every day, we create 2.5 quintillion bytes of data - so much that 90% of the data in the world today has been created in the last two years alone. this data comes from everywhere: sensors used to gather climate information, posts to social media sites, digital pictures and videos, purchase transaction records, and cell phone GPS signals to name a few. the IDC sizing of the digital universe - information that is either created or captured in digital form and then replicated in 2006 - is 161 Exabyte, growing to 988 Exabyte in 2010, representing a compound annual growth rate (CAGR) of 57%. A variety of system architectures have been implemented for data-intensive computing and large-scale data analysis applications including parallel and distributed relational database management systems which have been available to run on shared nothing clusters of processing nodes for more than two decades. However most data growth is with data in unstructured form and new processing paradigms with more flexible data models were needed. Several solutions have emerged including the MapReduce architecture pioneered by Google and now available in an open-source implementation called Hadoop used by Yahoo, Facebook, and others. 20% of the world's servers go into huge data centers by the “Big 5” - Google, Microsoft, Yahoo, Amazon, eBay [1].

关键词： File systems Google Computers Data processing Distributed databases Computational modeling Servers

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Cluster analysis for the cloud: parallel competitive fitness and parallel K-means++ for large dataset analysis

Cluster analysis for the cloud: Parallel competitive fitness...

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IEEE international conference on Cloud Computing Technology and Science (CloudCom)

作者： Rui Maximo Esteves thomas Hacker Chunming Rong Department of Electrical and Computer Engineering University of Stavanger Norway Department of Computer and Information Technology Purdue University West Lafayette USA

the amount of resources needed to provision Virtual Machines (VM) in a cloud computing systems to support virtual HPC clusters can be predicted from the analysis of historic use data. In previous work, Hacker et al. found that cluster analysis is a useful tool to understand the underlying spatio-temporal dependencies present in system fault and use logs. However, the cluster analysis used for reducing spatio-temporal dependences should be fast and accurate to understand the underlying stochastic properties of these systems. K-means is a fast cluster analysis method, in which accuracy depends on the use of initialization algorithms that are usually serial and slow. In this paper we present two new parallel strategies for fast seeding K-means cluster analysis. Both strategies were tested on a real problem where the aim was to reduce spatial and temporal dependencies of failures on large supercomputer systems. the performance of both strategies were compared with five existing serial implementations: K-means implementations of 1) Lloyd (L); 2) McQueen (M); and 3) Hartigan - Wong (HW), all of them using Forgy seeding; 4) K-means++; and 5) Neural Gas clustering (NG), a more recent and sophisticated method. Our results show that our new parallel Competitive Fitness approach reduces the Within Sum of Squares (WSQQ) measure, thus increasing cluster quality of the three K-means implementations: L; M; HW, and is 200 times faster than the existing serial K-means++. the existing serial and our new parallel K-means++ have the lowest WSQQ. Our new parallel K-means++ is twice as fast as the existing serial K-means++ method, and is 4 times faster than the NG method. Moreover, our new methods did not generate empty clusters, while NG did. As a result of our new techniques, predicting the amount of resources needed to provision VMs processing historic system fault and use data can now be done faster and with more accuracy.

关键词： Clustering algorithms Algorithm design and analysis Partitioning algorithms Cloud computing conferences Computer hacking Accuracy

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High Performance Database processing

High Performance Database Processing

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international conference on Advanced Information Networking and Applications (AINA)

作者： David Taniar Clayton School of Information Technology Monash University Clayton VIC Australia

the sizes of databases have seen exponential growth in the past, and such growth is expected to accelerate in the future, with the steady drop in storage cost accompanied by a rapid increase in storage capacity. Many years ago, a terabyte database was considered to be large, but nowadays they are sometimes regarded as small, and the daily volumes of data being added to some databases are measured in terabytes. In the future, petabyte and exabyte databases will be common. With such volumes of data, it is evident that the sequential processing paradigm will be unable to cope, for example, even assuming a data rate of 1 terabyte per second, reading through a petabyte database will take over 10 days. To effectively manage such volumes of data, it is necessary to allocate multiple resources to it, very often massively so. the processing of databases of such astronomical proportions requires an understanding of how high-performance systems and parallelism work. Besides the massive volume of data in the database to be processed, some data has been distributed across the globe in a Grid environment. these massive data centres are also a part of the emergence of Cloud computing, where data access has shifted from local machines to powerful servers hosting web applications and services, making data access across the Internet using standard web browsers pervasive. this adds another dimension to such systems. this talk, based on our recent published book [1], discusses fundamental understanding of parallelism in data-intensive applications, and demonstrates how to develop faster capabilities to support them. this includes the importance of indexing in parallel systems [2-4], specialized algorithms to support various query processing [5-9], as well as objectoriented scheme [10-12]. parallelism in databases has been around since the early 1980s, when many researchers in this area aspired to build large special-purpose database machines -- databases employing dedicated specialized

关键词： Distributed databases parallel processing Query processing Bioinformatics Algorithm design and analysis

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