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Advanced high speed parallel Frame Synchronizer for high data rate Indian Remote sensing satellite series

Advanced high speed Parallel Frame Synchronizer for high dat...

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international conference on Computers and Devices for Communication (CODEC)

作者： R. Srinivas P. V. V. Subba Rao L. Nithyanandan P. Naveen Kumar G. Umadevi Satellite Data Reception Systems National Remote Sensing Centre ISRO Hyderabad India Department of Electronics and Communication Engineering Pondicherry Engineering College Puducherry India Department of Electronics and Communication Engineering Osmania University Hyderabad India

ISBN: (纸本)9781467326193

the Video data from remote sensing satellite is transmitted serially frame after frame. To mark the beginning of video data a known unique code is embedded at the beginning of the video data frame. this is known as Frame Synchronizer code. Pseudo-Noise sequences are chosen as frame synchronizer codes as they are easy to generate, detect and have auto correlation property. Generally, for all Indian Remote sensing satellite series 127 bits Pseudo-Noise sequence is chosen as frame synchronizer code. On-board the satellite, the video data buffering is in serial fashion and for appropriate processing it is required to be formatted in data packets. Hence, data formatting is done onboard the satellite and then the Pulse Coded Modulated data is transmitted to ground station. the previous Indian Remote Sensing Satellites series has data rate of 105 Mbps. the Present data rate of Radar imaging satellite-1 (RISAT-1) is 640 MBps. In order to accommodate such high data rates in the limited bandwidths, the video data is transmitted in Right hand Circular Polarization (RHCP) and Left Hand Circular Polarization (LHCP). the QPSK modulation is used for video data transmission. Hence at such high data rates an advanced high speed frame synchronizer is required to cater to such high data rates. the advanced parallel processing technique of frame synchronism, detection and monitoring is unique as it doubles the operating frequency of the Frame synchronizer. Also with the same hardware, the frequency response of the hardware circuit can be doubled. If the maximum operating frequency is `f' Hz then using Advanced parallel Frame synchronizer technique, the operating frequency response is doubled to `2f' Hz using the same hardware chip. In this paper Advanced frame synchronizer circuit is been implemented and is put to use to archive video data from Indian Radar Imaging Satellite-1.

关键词： Advanced Frame synchronizer Pseudo-noise Sequence (PN sequence) Indian remote sensing satellites (IRS) Right hand circular polarization (RHCP) Left hand circular polarization (LHCP) Radar Imaging satellite (RISA T) video data Data transfer rates Synchronizer remote sensing satellites FRAMES Frame frequency response operating frequency maximum operating frequency

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Towards massively parallel simulations of massively parallel high-performance computing systems 12

Towards massively parallel simulations of massively parallel...

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Proceedings of the 5th international ICST conference on Simulation Tools and Techniques

作者： Robert Birke German Rodriguez Cyriel Minkenberg IBM Research -- Zurich Rüschlikon Switzerland

ISBN: (纸本)9781450315104

the power of high-performance computing (HPC) is applied to simulate highly complex systems and processes in many scientific communities, e. g. in particle physics, weather and climate research, bio-sciences, materials science, pharmaceutics, astronomy, or *** HPC systems are so complex that the design of such a system, including architecture design space exploration and performance prediction, requires HPC-like simulation capabilities. To this end, we developed an Omnest-based simulation environment that enables studying the impact of an HPC machine's communication subsystem on the overall system's performance for specific *** the scale of current high-end HPC systems is in the range of hundreds of thousands of processing cores, full system simulation---at an abstraction level that still maintains a reasonably high level of detail---is infeasible without resorting to parallel simulation, the main limiting factors being simulation run time and memory *** describe our experiences in adapting our simulation environment to take advantage of the parallel distributed simulation capabilities provided by Omnest. We present results obtained on a many-core SMP machine as well as a small-scale InfiniBand ***, we ported our simulation environment, including Omnest itself, to the massively parallel IBM Blue Gene®/P platform. We report results from initial experiments on this platform using up to 512 cores in parallel.

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Efficient Computation of Spherical Harmonic Transform using parallel Architecture of CUDA

Efficient Computation of Spherical Harmonic Transform using ...

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5th international conference on Signal processing and Communication Systems (ICSPCS)

作者： Huang, Weiyu Khalid, Zubair Kennedy, Rodney A. Australian Natl Univ Coll Engn & Comp Sci Res Sch Engn Canberra ACT Australia

ISBN: (纸本)9781457711800

Spherical harmonics serve as basis functions on the unit sphere and spherical harmonic transform is required in analysis and processing of signals in the spectral domain. We investigate the possibility of parallel computation of spherical harmonic transform using Compute Unified Device Architecture (CUDA) with no communication between parallel kernels. We identify the parallel components in the widely used spherical harmonic transform method proposed by Driscoll and Healy. We provide the implementation details and compare the computational complexity with the sequential algorithm. For a given bandlimited signal with maximum spherical harmonics degree L, using the O(L) number of parallel processing kernels, we present that the spherical harmonic coefficients can be calculated in O(Llog(2) L) time as compared to O(L-2 log(2) L). For corroboration, we provide the simulation results using CUDA which indicate the reduction in computational complexity

关键词： parallel architectures spherical harmonic analysis Sphericity complexity classes Transform parallel processing (COMPUTERS) sequential algorithm Spectral domain Simulation results

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Improving the parallel Schnorr-Euchner LLL Algorithm

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Backes, Werner Wetzel, Susanne Stevens Inst Technol Hoboken NJ 07030 USA

ISBN: (纸本)9783642246494

this paper introduces a number of modifications that allow for significant improvements of parallel LLL reduction. Experiments show that these modifications result in an increase of the speed-up by a factor of more than 1.35 for SVP challenge type lattice bases in comparing the new algorithm with the state-of-the-art parallel LLL algorithm.

关键词： Computers

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Performance evaluation of parallel multi-objective particle swarm optimization

Performance evaluation of parallel multi-objective particle ...

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5th Indian international conference on Artificial Intelligence, IICAI 2011

作者： Arun, Jambhlekar Pushkar IIT Roorkee India

ISBN: (纸本)9780972741286

Most of the real-world optimization problems are NP-hard and compute intensive. To solve such problems, meta-heuristic based approach such as evolutionary algorithms tackle problem of NP-hardness and parallel implementation tackles issue of compute-intensiveness. However, for parallel implementation of algorithms, selecting appropriate platform is necessity as it affects the overall cost. Because of the accuracy and easiness, to solve the optimization problems, Particle swarm optimization (PSO) gained ample attention of researchers over the decade. In this paper, I have focused on the parallel implementation of multi-objective PSO on cluster and GPU. Based on the nature of fitness function and parameters of algorithms, this paper evaluates the performance of MOPSO.

关键词： Graphics processing unit

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Comparison of three parallel Point-Multiplication algorithms on Conic Curves

Comparison of Three Parallel Point-Multiplication Algorithms...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Li, Yongnan Xiao, Limin Qin, Guangjun Li, Xiuqiao Lei, Songsong Beihang Univ State Key Lab Software Dev Environm Beijing 100191 Peoples R China

ISBN: (纸本)9783642246685

this paper makes a comparison of three parallel point-multiplication algorithms on conic curves over ring Zn. We propose one algorithm for paralleling point-multiplication by utilizing Chinese Remainder theorem to divide point-multiplication over ring Zn into two different point-multiplications over finite field and to compute them respectively. Time complexity and speedup ratio of this parallel algorithm are computed on the basis of our previous research about the basic parallel algorithms in conic curves cryptosystem. A quantitative performance analysis is made to compare this algorithm with two other algorithms we designed before. the performance comparison demonstrates that the algorithm presented in this paper can reduce time complexity of point-multiplication on conic curves over ring Zn and it is more efficient than the preceding ones.

关键词： conic curves ring Zn finite field Fp point-addition point-double point-multiplication Chinese Remainder theorem

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A Combined Arithmetic Logic Unit and Memory Element for the Design of a parallel Computer

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Rahman, Mohammed Ziaur Univ Malaya Dept Comp Sci & Technol Kuala Lumpur 50603 Malaysia

ISBN: (纸本)9783642246494

Memory-CPU single communication channel bottleneck of the von Neumann architecture is quickly stalling the growth of computer processors. A probable solution to this problem is to fuse processing and memory elements. A simple low latency single on-chip memory and processor cannot solve the problem as the fundamental channel bottleneck will still be there due to the logical splitting of processor and memory. this paper presents that a paradigm shift is possible by combining Arithmetic logic unit and Random Access Memory (ARAM) elements at bit level. this bit level modest ARAM is used to perform word level ALU instructions with minor modifications. this makes the ARAM cells capable of executing instructions in parallel. It is also asynchronous and hence reduces power consumption significantly. A CMOS implementation is presented that verifies the practicality of the proposed ARAM.

关键词： Computer architectures parallel architectures Memory architectures

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Massively parallel Identification of Intersection Points for GPGPU Ray Tracing

Massively Parallel Identification of Intersection Points for...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M. G. Jozwiak, Lech Univ Fed Rio de Janeiro LAM Comp Architecture & Microeletron Lab Syst Engn & Comp Sci Program COPPE BR-21941 Rio De Janeiro Brazil Univ Estado Rio de Janeiro Fac Engn Dept Elect Engn & Telecommun Rio De Janeiro Brazil Eindhoven Univ Technol Dept Elect Engn Elect Syst Eindhoven Netherlands

ISBN: (纸本)9783642246685

the latest advancements in computer graphics architectures, as the replacement of some fixed stages of the pipeline for programmable stages (shaders), have been enabling the development of parallel general purpose applications on massively parallel graphics architectures (Streaming Processors). For years the graphics processing unit (GPU) is being optimized for increasingly high throughput of massively parallel floating-point computations. However, only the applications that exhibit Data Level parallelism can achieve substantial acceleration in such architectures. In this paper we present a parallel implementation of the GridRT architecture for GPGPU ray tracing. Such architecture can expose two levels of parallelism in ray tracing: parallel ray processing and parallel intersection tests, respectively. We also present a traditional parallel implementation of ray tracing in GPGPU, for comparison against the GridRT-GPGPU implementation.

关键词： Ray tracing

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High performance content-based matching using GPUs 11

High performance content-based matching using GPUs

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Proceedings of the 5th ACM international conference on Distributed event-based system

作者： Margara, Alessandro Cugola, Gianpaolo Dip. di Elettronica e Informazione Politecnico di Milano Milano Italy

ISBN: (纸本)9781450309059

Matching incoming event notifications against received subscriptions is a fundamental part of every publish-subscribe infrastructure. In the case of content-based systems this is a fairly complex and time consuming task, whose performance impacts that of the entire system. In the past, several algorithms have been proposed for efficient content-based event matching. While they differ in most aspects, they have in common the fact of being conceived to run on conventional, sequential hardware. On the other hand, modern Graphical processing Units (GPUs) offer off-the-shelf, highly parallel hardware, at a reasonable cost. Unfortunately, GPUs introduce a totally new model of computation, which re- quires algorithms to be fully re-designed. In this paper, we describe a new content-based matching algorithm designed to run efficiently on CUDA, a widespread architecture for general purpose programming on GPUs. A detailed comparison with SFF, the matching algorithm of Siena, known for its efficiency, demonstrates how the use of GPUs can bring impressive speedups in content-based matching. At the same time, this analysis demonstrates the peculiar aspects of CUDA programming that mostly impact performance. © 2011 ACM.

关键词： parallel architectures

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Particle-In-Cell algorithms for Plasma simulations on heterogeneous architectures

Particle-In-Cell algorithms for Plasma simulations on hetero...

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19th international Euromicro conference on parallel, Distributed and Network-Based processing (PDP)

作者： Saez, Xavier Soba, Alejandro Cela, Jose M. Sanchez, Edilberto Castejon, Francisco CNS BSC Comp Applicat Sci & Engn Barcelona Spain CIEMAT Lab Nacl Fus Madrid Spain

ISBN: (纸本)9780769543284

Within the fusion community, a large number of codes are in use to simulate various aspects of the plasma behaviour. Many codes have been written by physicists with a big emphasis on the physics without using the latest technologies available in computer science. For improving this situation, a project with acronym EUFORIA [1] was created. the main target of this project is to increase the performance of key existing codes, either parallelizing the sequential codes or improving their parallelization. However, in general these codes were not thought for new supercomputers based on muticore architectures and only take advantage of the task level parallelism, basically using Message Passing Interface (MPI). In this paper we discuss several possible ways to apply hybrid parallelization techniques in fusion codes for exploiting new multiprocessor supercomputers under development.

关键词： PIC HPC hybrid code Petascaling machines

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