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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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Generic parallel Genetic Algorithm Framework for Protein Optimisation

Generic Parallel Genetic Algorithm Framework for Protein Opt...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Folkman, Lukas Pullan, Wayne Stantic, Bela Griffith Univ Inst Integrated & Intelligent Syst Nathan Qld 4111 Australia

ISBN: (纸本)9783642246685

Proteins are one of the most vital macromolecules on the cellular level. In order to understand the function of a protein, its structure needs to be determined. For this purpose, different computational approaches have been introduced. Genetic algorithms can be used to search the vast space of all possible conformations of a protein in order to find its native structure. A framework for design of such algorithms that is both generic, easy to use and performs fast on distributed systems may help further development of genetic algorithm based approaches. We propose such a framework based on a parallel master-slave model which is implemented in C++ and Message Passing interface. We evaluated its performance on distributed systems with a different number of processors and achieved a linear acceleration in proportion to the number of processing units.

关键词： parallel Genetic Algorithm Protein Optimisation Protein Structure Prediction

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parallel Implementation of External Sort and Join Operations on a Multi-core Network-Optimized System on a Chip

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Khorasani, Elahe Paulovicks, Brent D. Sheinin, Vadim Yeo, Hangu IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9783642246494

In a commercial Relational Database Management System (RDBMS), sort and join are the most demanding operations, and it is quite beneficial to improve the performance of external sort and external join algorithms that handle large input data sizes. this paper proposes parallel implementations of multithreaded external sort and external hash join algorithms to accelerate IBM DB2, one of leading RDBMSs, using an IBM Power Edge of Network (IBM PowerEN (TM)) Peripheral Component Interconnect Express (PCIe) card as an accelerator. the preliminary results show that the proposed parallel implementation of the algorithms on PowerEN (TM) PCIe card can speed up the DB2 sort and join performance about two times.

关键词： Sort Join Relational Database

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Emotional Contribution Process Implementations on parallel Processors

Emotional Contribution Process Implementations on Parallel P...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Dominguez, Carlos Hassan, Houcine Albaladejo, Jose Marco, Maria Crespo, Alfons Univ Politecn Valencia Dept Informat Sistemas & Comp E-46071 Valencia Spain

ISBN: (纸本)9783642246685

An emotional agent software architecture for real-time mobile robotic applications has been developed. In order to allow the agent to undertake more dynamically constrained application problem solving, the processor computation time should be reduced and the gained time is used for executing more complex processes. In this paper, the response time of the operating processes, in each attention cycle of the agent, is decreased by parallelizing the highly parallel processes of the architecture, namely, emotional contribution processes. the implementation of these processes has been evaluated in Field Programmable Gate Array (FPGA) and multicore processors.

关键词： FPGA Multicore Load balancing Robotics Agents Real-time

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FPGA Technology And parallel Computing Towards Automatic Microarray Image processing

FPGA Technology And Parallel Computing Towards Automatic Mic...

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34th international conference on Telecommunications and Signal processing (TSP)

作者： Belean, Bogdan Borda, Monica LeGal, Bertrand Malutan, Raul Tech Univ Cluj Napoca Dept Commun 26-28 George Baritiu St Cluj Napoca 400027 Romania Univ Bordeaux Integrat Materiaux Syst Lab IMS Bordeaux France

ISBN: (纸本)9781457714115

Automation, computational time and cost are open subjects in microarray image processing. the present paper proposes image processing techniques together with their implementations in order to eliminate the shortcomings of the existing software platforms for microarray image processing: user intervention, increased computational time and cost. thus, for each step of microarray image processing, application-specific hardware architectures are designed aiming algorithms parallelization for fast processing. Computational time is estimated and compared with state of the art approaches. the proposed hardware architectures integrated inside microarray scanners deliver microarray image characteristics in an automated manner, excluding the need of an additional software platform. the FPGA technology was chosen for implementation, due to its parallel computation capabilities and ease of reconfiguration.

关键词： Microarray image processing parallel computing

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Fast adaptive ultrasound speckle reduction with bilateral filter on CUDA

Fast adaptive ultrasound speckle reduction with bilateral fi...

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5th international conference on Bioinformatics and Biomedical Engineering, iCBBE 2011

作者： Jiang, Fengjiao Shi, Dan Liu, Dong C. Computer Science College Sichuan University Chengdu China

ISBN: (纸本)9781424450893

the Compute Unified Device Architecture (CUDA) is a new parallel processing platform making use of the unified shader design of the most current Graphics processing Units (GPUs) from NVIDIA. In this paper, we apply this revolutionary new technology to implement the speckle reduction with adaptive bilateral filter for medical ultrasound imaging. the parallel speckle detection and mask producing with space for time algorithms are also presented. this bilateral filter method achieves a frame rate of 30 fps for the 256×512 image with once iteration, about 44 times faster than the CPU implementation. Testing results from GPU and CPU are compared in terms of visual image quality and program runtime with different image sizes. © 2011 IEEE.

关键词： Graphics processing unit

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Distributed Load Balancing for parallel Agent-based Simulations

Distributed Load Balancing for Parallel Agent-based Simulati...

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19th international Euromicro conference on parallel, Distributed and Network-Based processing (PDP)

作者： Cosenza, Biagio Cordasco, Gennaro De Chiara, Rosario Scarano, Vittorio Univ Salerno ISISLab Dip Informat & Applicaz Renato M Capocelli I-84084 Fisciano SA Italy

ISBN: (纸本)9780769543284

We focus on agent-based simulations where a large number of agents move in the space, obeying to some simple rules. Since such kind of simulations are computational intensive, it is challenging, for such a contest, to let the number of agents to grow and to increase the quality of the simulation. A fascinating way to answer to this need is by exploiting parallel architectures. In this paper, we present a novel distributed load balancing schema for a parallel implementation of such simulations. the purpose of such schema is to achieve an high scalability. Our approach to load balancing is designed to be lightweight and totally distributed: the calculations for the balancing take place at each computational step, and influences the successive step. To the best of our knowledge, our approach is the first distributed load balancing schema in this context. We present both the design and the implementation that allowed us to perform a number of experiments, with up-to 1, 000, 000 agents. Tests show that, in spite of the fact that the load balancing algorithm is local, the workload distribution is balanced while the communication overhead is negligible.

关键词： Distributed Computing parallel algorithms Behavioral Simulations

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HLPP'11 - Proceedings of the 5th international Workshop on High-Level parallel Programming and Applications

HLPP'11 - Proceedings of the 5th International Workshop on H...

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5th ACM SIGPLAN Workshop on High-Level parallel Programming and Applications, HLPP 2011

ISBN: (纸本)9781450308625

the proceedings contain 4 papers. the topics discussed include: cache size in a cost model for heterogeneous skeletons;an efficient skew-insensitive algorithm for join processing on grid architectures;formally specifying and analyzing a parallel virtual machine for lazy functional languages using Maude;and type system for a safe execution of parallel programs in BSML.

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Efficient Decoding of QC-LDPC Codes Using GPUs

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhao, Yue Chen, Xu Sham, Chiu-Wing Tam, Wai M. Lau, Francis C. M. Hong Kong Polytech Univ Elect & Informat Engn Dept Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9783642246494

In this work, we propose an efficient quasi-cyclic LDPC (QC-LDPC) decoder simulator which runs on graphics processing units (GPUs). We optimize the data structures of the messages used in the decoding process such that both the read and write processes can be performed in a highly parallel manner by the GPUs. We also propose a highly efficient algorithm to convert the data structure of the messages from one form to another with very little latency. Finally, with the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based LDPC decoder is found to run at around 100 times faster than a CPU-based simulator.

关键词： Belief propagation CUDA graphics processing unit (GPU) low-density parity-check codes LDPC decoder

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Density-based Hardware-oriented Classification for Spike Sorting Microsystems

Density-based Hardware-oriented Classification for Spike Sor...

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5th international IEEE Engineering-in-Medicine-and-Biology-Society (EMBS) conference on Neural Engineering (NER)

作者： Cheng, Li-Fang Chen, Tung-Chien Chang, Nai-Fu Chen, Liang-Gee Natl Taiwan Univ Dept Elect Engn Taipei 10764 Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei 10764 Taiwan

ISBN: (纸本)9781424441419

Successful proof-of-concept laboratory experiments on cortically-controlled brain computer interface motivate continued development for neural prosthetic microsystems (NPMs). One of the research directions is to realize realtime spike sorting processors (SSPs) on the NPM. the SSP detects the spikes, extracts the features, and then performs the classification algorithm in realtime in order to differentiate the spikes for the different firing neurons. Several architectures have been designed for the spike detection and feature extraction. However, the classification hardware is missing. To complete the SSP, a density-based hardware-oriented classification algorithm is proposed for hardware implementation. the traditional classification algorithms require a considerable memory space to store all the training features during the processing iteration, which results in a considerable power and area for the hardware. the proposed one is designed based on the density map of the spike features. the density map can be accumulated on-line with the coming of the spike features. therefore the algorithm can save significant memory space, and is good for efficient hardware implementation.

关键词： Algorithm design and analysis Clustering algorithms Feature extraction Hardware Memory management Sorting Training brain-computer interfaces classification algorithm cortically-controlled brain computer interface density-based hardware-oriented classification feature extraction feature extraction firing neurons hardware-oriented classification medical signal detection medical signal processing neural prosthetic microsystems neurophysiology prosthetics signal classification spike sorting microsystems spike sorting processors

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Binary Addition Chain on EREW PRAM

Binary Addition Chain on EREW PRAM

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Fathy, Khaled A. Bahig, Hazem M. Bahig, Hatem M. Ragb, A. A. Sinai Univ Fac Engn Dept Basic Sci Cairo Egypt Ain Shams Univ Fac Sci Dept Math Div Comp Sci Cairo Egypt Al Azhar Univ Fac Sci Dept Math Cairo Egypt

ISBN: (纸本)9783642246685

An addition chain for a natural number x of n bits is a sequence of numbers a(0), a(1), ... , a(l), such that a(0) = 1, a(l) = x, and a(k) = a(i) + a(j) with 0 <= i, j < k <= l. the addition chain problem is what is the minimal number of additions needed to compute X starting from 1? In this paper, we present a new parallel algorithm to generate a short addition chain for x. the algorithm has running time O(log(2) n) using polynomial number processors under EREW PRAM (exclusive read exclusive write parallel random access machine). the algorithm is faster than previous algorithms and is based on binary method.

关键词： Addition chain binary method parallel algorithm EREW PRAM

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