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Case study of efficient parallel memory access programming for the embedded heterogeneous multicore DSP architecture ePUMA

Case study of efficient parallel memory access programming f...

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5th international conference on Complex, Intelligent and Software Intensive Systems, CISIS 2011

作者： Hansson, Erik Sohl, Joar Kessler, Christoph Liu, Dake Dept. of Computer and Information Science Linköpings Universitet Sweden Dept. of Electrical Engineering Linköpings Universitet Sweden

ISBN: (纸本)9780769543734

We consider the challenges in writing efficient code for ePUMA, a novel domain-specific heterogeneous multicore architecture with SIMD DSP slave cores, multi-banked on-chip vector register files for parallel access and configurable permutation hardware that decouples memory access from computation. Suitable data layout in memory and in vector registers, combined with using ePUMA's powerful addressing modes, is key to exploiting SIMD units efficiently and achieving the throughput required for prospective applications in 4G mobile telecommunication and multimedia. © 2011 IEEE.

关键词： Digital signal processing

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Scaling HMMER performance on multicore architectures

Scaling HMMER performance on multicore architectures

引用

5th international conference on Complex, Intelligent and Software Intensive Systems, CISIS 2011

作者： Isaza, Sebastian Houtgast, Ernst Sanchez, Friman Ramirez, Alex Gaydadjiev, Gergi Computer Engineering Laboratory Delft University of Technology Netherlands Computer Architecture Department Technical University of Catalonia Spain Barcelona Supercomputing Center Spain

ISBN: (纸本)9780769543734

In bioinformatics, protein sequence alignment is one of the fundamental tasks that scientists perform. Since the growth of biological data is exponential, there is an ever-increasing demand for computational power. While current processor technology is shifting towards the use of multicores, the mapping and parallelization of applications has become a critical issue. In order to keep up with the processing demands, applications' bottlenecks to performance need to be found and properly addressed. In this paper we study the parallelism and performance scalability of HMMER, a bioinformatics application to perform sequence alignment. After our study of the bottlenecks in a HMMER version ported to the Cell processor, we present two optimized versions to improve scalability in a larger multicore architecture. We use a simulator that allows us to model a system with up to 512 processors and study the performance of the three parallel versions of HMMER. Results show that removing the I/O bottleneck improves performance by 3X and 2.4X for a short and a long HMM query respectively. Additionally, by offloading the sequence pre-formatting to the worker cores, larger speedups of up to 27X and 7X are achieved. Compared to using a single worker processor, up to 156X speedup is obtained when using 256 cores. © 2011 IEEE.

关键词： Bioinformatics

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A decision model to select the optimal storage architecture for relational databases

A decision model to select the optimal storage architecture ...

引用

2011 5th international conference on Research Challenges in Information Science, RCIS 2011

作者： Lübcke, Andreas Köppen, Veit Saake, Gunter School of Computer Science Otto-von-Guericke-University Magdeburg Germany

ISBN: (纸本)9781424486694

Requirements for database systems differ from small-scale database programs for embedded devices with minimal footprint to large-scale on-line analytical processing applications. For relational database management systems, two storage architectures have been introduced: a) row-oriented architecture and b) column-oriented architecture. In this paper, we present a query decomposition approach to evaluate database operations with respect to their performance according to the storage architecture. We map decomposed queries to workload patterns which contain aggregated database statistics. Further, we develop our complementary decision models which advise the selection of the optimal storage architecture for a given application domain. the first decision model improves the performance of running systems (on-line). the second and third decision model advise an efficient database design or decide which architecture is more suitable for a given application domain (off-line). © 2011 IEEE.

关键词： Query processing

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GVT algorithms and discrete event dynamics on 129K processor cores

GVT algorithms and discrete event dynamics on 129K processor...

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18th international conference on High Performance Computing, HiPC 2011

作者： Perumalla, Kalyan S. Park, Alfred J. Tipparaju, Vinod Oak Ridge National Laboratory Oak Ridge TN United States

ISBN: (纸本)9781457719516

parallel discrete event simulation (PDES) represents a class of codes that are challenging to scale to large number of processors due to tight global timestamp-ordering and fine-grained event execution. One of the critical factors in scaling PDES is the efficiency of the underlying global virtual time (GVT) algorithm needed for correctness of parallel execution and speed of progress. Although many GVT algorithms have been proposed previously, few have been proposed for scalable asynchronous execution and none customized to exploit one-sided communication. Moreover, the detailed performance effects of actual GVT algorithm implementations on large platforms are unknown. Here, three major GVT algorithms intended for scalable execution on high-performance systems are studied: (1) a synchronous GVT algorithm that affords ease of implementation, (2) an asynchronous GVT algorithm that is more complex to implement but can relieve blocking latencies, and (3) a variant of the asynchronous GVT algorithm, proposed and studied for the first time here, to exploit one-sided communication in extant supercomputing platforms. Performance results are presented of implementations of these algorithms on up to 129,024 cores of a Cray XT5 system, exercised on a range of parameters: optimistic and conservative synchronization, fine-to medium-grained event computation, synthetic and non-synthetic applications, and different lookahead values. Performance to the tune of tens of billions of events executed per second are registered, exceeding the speeds of any known PDES engine, and showing asynchronous GVT algorithms to outperform state-of-the-art synchronous GVT algorithms. Detailed PDES-specific runtime metrics are presented to further the understanding of tightly-coupled discrete event dynamics on massively parallel platforms. © 2011 IEEE.

关键词： parallel processing systems

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Target Container: A Target-Centric parallel Programming Abstraction for Video-based Surveillance

Target Container: A Target-Centric Parallel Programming Abst...

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13th international conference on Advanced Concepts for Intelligent Vision Systems (ACIVS) / 5th ACM/IEEE international conference on Distributed Smart Cameras (ICDSC)

作者： Hong, Kirak Smaldone, Stephen Shin, Junsuk Lillethun, David Iftode, Liviu Ramachandran, Umakishore Georgia Inst Technol Atlanta GA 30332 USA Rutgers State Univ New Brunswick NJ USA

ISBN: (纸本)9781457717079

We introduce a novel abstraction, the target container (TC), which serves as a parallel programming model and execution framework for developing complex applications for tracking multiple targets in a large-scale camera network. the key insight is to allow the domain expert (e.g., a vision researcher) to focus on the algorithmic details of target tracking and let the system deal with providing the computational resources (cameras, networking, and processing) to enable target tracking. Each TC has a one-to-one correspondence with a target, possibly tracked from multiple cameras. the domain expert provides the code modules for target tracking (such as detectors and trackers) as handlers to the TC system. the handlers are invoked dynamically by the TC system to discover new targets (detector) and to follow existing targets (tracker). the TC system also provides an interface for merging TCs whenever they are determined to be corresponding to the same target. this paper presents the design of the TC system, details of an experimental prototype, and an example application to demonstrate the simplicity of using the TC programming model.

关键词： Cameras Computational modeling Data structures Detectors Programming Surveillance Target tracking

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Approximating quantified SMT-solving with SAT

Approximating quantified SMT-solving with SAT

引用

international conference on Secure Software Integration and Reliability Improvement Companion

作者： Fu, Xianjin Liu, Wanwei Li, Jing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769544540

Satisfiability Modulo theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems. © 2011 IEEE.

关键词： Model checking

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Hardware and Software Tradeoffs for Task Synchronization on Manycore architectures

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17th international Euro-Par conference on parallel processing

作者： Yan, Yonghong Chatterjee, Sanjay Orozco, Daniel A. Garcia, Elkin Budimlic, Zoran Shirako, Jun Pavel, Robert S. Gao, Guang R. Sarkar, Vivek Rice Univ Dept Comp Sci Houston TX 77251 USA Univ Delaware Dept Elect Engn Newark DE USA

ISBN: (纸本)9783642233975

Manycore architectures - hundreds to thousands of cores per processor - are seen by many as a natural evolution of multicore processors. To take advantage of this massive parallelism in practice requires a productive parallel programming model, and an efficient runtime for the scheduling and coordination of concurrent tasks. A critical prerequisite for an efficient runtime is a scalable synchronization mechanism to support task coordination at different levels of granularity. this paper describes the implementation of a high-level synchronization construct called phasers on the IBM Cyclops64 manycore processor, and compares phasers to lower-level synchronization primitives currently available to Cyclops64 programmers. Phasers support synchronization of dynamic tasks by allowing tasks to register and deregister with a phaser object. It provides a general unification of point-to-point and collective synchronizations with easy-to-use interfaces, thereby offering productivity advantages over hardware primitives when used on manycores. We have experimented with several approaches to phaser implementation using software, hardware and a combination of both to explore their portability and performance. the results show that a highly-optimized phaser implementation delivered comparable performance to that obtained with lower-level synchronization primitives. We also demonstrate the success of the hardware optimizations proposed for phasers.

关键词： Synchronization

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An Efficient Nested Query processing for Distributed Database Systems

An Efficient Nested Query Processing for Distributed Databas...

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5th international conference on Convergence and Hybrid Information Technology (ICHIT)

作者： Kang, Yu-Jin Choi, Chi-Hawn Yang, Kyung-En Kim, Hun-Gi Choi, Wan-Sup Chungbuk Natl Univ Dept Management Informat Syst U BIZ BK21 Cheongju South Korea Chungbuk Natl Univ Dept Bio Informat Technol Cheongju South Korea

ISBN: (纸本)9783642241055;9783642241062

Performance of OLAP queries becomes a critical issue as the amount of data in the data warehouses increases rapidly. To solve this performance issue, we proposed a high performance database cluster system called HyperDB in which many PCs can be mobilized for excellent performance. In HyperDB, an OLAP query can be decomposed into sub-queries, and each of the sub-queries can be processed independently on a PC in a short time. But if an OLAP query has nested form (i.e., nested SQL), it could not be decomposed into sub-queries. In this paper, we propose a parallel distributed query processing algorithm for nested queries in HyperDB system. Traditionally, parallel distributed processing of nested queries is known as a difficult problem in the database area.

关键词： Distributed Database System Data Warehouse OLAP Query parallel Distributed processing Nested Query

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TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-core Hybrid Transact...

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IEEE 19th Annual international Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sonmez, Nehir Arcas, Oriol Pflucker, Otto Unsal, Osman S. Cristal, Adrian Hur, Ibrahim Singh, Satnam Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Spanish Natl Res Council Madrid Spain Microsoft Res Cambridge Cambridge England

ISBN: (纸本)9780769543017

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

关键词： Field programmable gate arrays Hardware MIPS R3000-compatible core MPSoC Multicore processing Proposals Registers Software TMbox TinySTM-ASF Virtex-5 FPGA electronic engineering computing field programmable gate arrays flexible 16-core hybrid transactional memory system flexible system logic design multicore design space multicore prototyping multiprocessing systems parallel programming parallel programming reconfigurable 16-core hybrid transactional memory system reconfigurable architectures reconfigurable computing system-on-chip transactional memory

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Implementation of parallel Image processing Using NVIDIA GPU Framework

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international conference on Advances in Computing, Communication and Control (ICAC3)

作者： Daga, Brijmohan Bhute, Avinash Ghatol, Ashok Fr Conceicao Rodrigues Coll Engn Bombay Maharashtra India V J T I Bombay Maharashtra India D Y Patil Grp Inst Pune Maharashtra India

ISBN: (纸本)9783642184390

We introduced a real time Image processing technique using modern programmable Graphic processing Units (GPU) in this paper. GPU is a SIMD (Single Instruction, Multiple Data) device that is inherently data-parallel. By utilizing NVIDIA's new GPU Programming framework, "Compute Unified Device Architecture" (CUDA) as a computational resource, we realize significant acceleration in the computations of different Image processing algorithms. Here we present an efficient implementation of algorithms on the NVIDIA GPU. Specifically, we demonstrate the efficiency of our approach by a parallelization and optimization of the algorithm. In result we show time comparison between CPU and GPU implementation.

关键词： GPU CUDA Image blending

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