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Using GPU to exploit parallelism on cryptography

Using GPU to exploit parallelism on cryptography

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Iberian conference on Information Systems and Technologies (CISTI)

作者： Renan Correa Detomini Renata Spolon Lobato Roberta Spolon Marcos Antonio Cavenaghi Departamento de Ciências de Computação e Estatística Universidade Estadual Paulista (UNESP) Sao Jose do Rio Brazil Departamento de Computação FC Universidade Estadual Paulista (UNESP) Bauru Brazil

In this article we explore the NVIDIA graphical processing units (GPU) computational power in cryptography using CUDA (Compute Unified Device Architecture) technology. CUDA makes the general purpose computing easy using the parallel processing presents in GPUs. To do this, the NVIDIA GPUs architectures and CUDA are presented, besides cryptography concepts. Furthermore, we do the comparison between the versions executed in CPU with the parallel version of the cryptography algorithms Advanced Encryption Standard (AES) and Message-digest Algorithm 5 (MD5) wrote in CUDA.

关键词： Graphics processing unit Computer architecture Encryption Central processing Unit Hardware

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Efficient GPGPU-Based parallel Packet Classification

Efficient GPGPU-Based Parallel Packet Classification

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IEEE international conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Che-Lun Hung Hsiao-Hsi Wang Shih-Wei Guo Yaw-Ling Lin Kuan-Ching Li Department of Computer Science and Communication Engineering Providence University Taichung Taiwan Department of Computer Science and Information Engineering Providence University Taichung Taiwan Department of Computer Science and Information Management Providence University Taichung Taiwan

With the rapid growth of network technologies, many new web services have been developed to provide various applications and computing functions. these services rely deeply on the internet. therefore, packet classification is an important issue of network security that typically adopts a flexible packet filtering system to classify each processed packet. Traditional packet classification requires hung computing time to process large amount of internet packets. Hence, we propose a GPGPU-based parallel packet classification method to decrease the computational cost. We also evaluate the performance of the proposed method with implementation on various memory architectures of CUDA device. the experiment results demonstrate that the proposed method can achieve significant speed up over the sequential packet classification algorithms on single CPU.

关键词： Graphics processing unit Registers Instruction sets Filtering algorithms Classification algorithms Band pass filters Memory architecture

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Power-Performance Comparison of Single-Task Driven Many-Cores

Power-Performance Comparison of Single-Task Driven Many-Core...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Fuat Keceli Tali Moreshet Uzi Vishkin Department of Electrical and Computer Engineering University of Maryland USA Department of Engineering Swarthmore College USA

Many-cores, processors with 100s of cores, are becoming increasingly popular in general-purpose computing, yet power is a limiting factor in their performance. In this paper, we compare the power and performance of two design points in the many-core processor domain. the XMT general-purpose processor provides significant runtime advantage on irregular parallel programs (e.g., graph algorithms). this was previously demonstrated and tied to its architecture choices and ease-of-programming. In contrast, current commercial GPUs excel at regular parallel programs that require high processing capability. In this work, we set the power envelope as a constraint and evaluate an envisioned 1024-core XMT processor against an NVIDIA GTX280 GPU considering various scenarios for estimating the power of the XMT chip. Even under worst-case assumptions and scenarios, simulations show that the XMT processor sustains its advantage over the GPU on irregular parallel programs, while not falling significantly behind on regular programs. the total energy spent per benchmark fits a similar pattern. Given that the two architectures target different types of parallelism, a future system can potentially utilize an XMT chip and a GPU chip in complementary roles.

关键词： Benchmark testing Graphics processing unit Computer architecture Temperature measurement Clocks Random access memory

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Adaptive parallel Interval Global Optimization algorithms Based on their Performance for Non-dedicated Multicore architectures

Adaptive Parallel Interval Global Optimization Algorithms Ba...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： J.F. Sanjuan Estrada L.G. Casado I. García Universidad de Almeria Almeria AndalucÃa ES Department of Computer Architecture and Electronics University of Almeria Almería Spain Department of Computer Architecture University of Mälaga Mälaga Spain

Branch and Bound (B&B) algorithms are highly parallelizable but they are irregular and dynamic load balancing techniques have been used to avoid idle processors. In previous work, authors use a dynamic number of threads at run time, which depends on the measured performance of the application for just one interval B&B algorithm running on the system. In this way, load balancing is achieved by thread generation decisions. In this work, we extend the study of these models to non-dedicated systems. In order to have a controlled test bed and comparable results, several instances of the interval global optimization algorithm are executed in the system, with the same model and problem to solve. therefore, a non-dedicated system is simulated because the execution of one application affects the execution of the other instances. this paper discusses different methods and models to decide when a thread should be created. Experiments show which of the proposed methods performs best in terms of maximum running time per application, using the fewest running threads. Following this parallel programming methodology, which is well suited for other B&B codes, applications can adapt their parallelism level to their performance and load of the system(at run time). this work represents a step forward towards increasing the performance of parallel algorithm running in non-dedicated and heterogeneous systems. the adaptive model discussed in this work is able to reduce the overall execution time for a set of instances of the same application running simultaneously. It also exempts the user from specifying the number of threads each application should use.

关键词： Instruction sets Kernel Computational modeling Adaptation model Load modeling parallel processing

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P2G: A Framework for Distributed Real-Time processing of Multimedia Data

P2G: A Framework for Distributed Real-Time Processing of Mul...

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international conference on parallel processing Workshops (ICPPW)

作者： Havard Espeland Paul B. Beskow Hakon K. Stensland Preben N. Olsen Stale Kristoffersen Carsten Griwodz Pal Halvorsen Department of Informatics Norway Simula Research Laboratory University of Oslo Norway

the computational demands of multimedia data processing are steadily increasing as consumers call for progressively more complex and intelligent multimedia services. New multi-core hardware architectures provide the required resources, but writing parallel, distributed applications remains a labor-intensive task compared to their sequential counter-part. For this reason, Google and Microsoft implemented their respective processing frameworks MapReduce and Dryad, as they allow the developer to think sequentially, yet benefit from parallel and distributed execution. An inherent limitation in the design of these batch processing frameworks is their inability to express arbitrarily complex workloads. the dependency graphs of the frameworks are often limited to directed acyclic graphs, or even pre-determined stages. this is particularly problematic for video encoding and other algorithms that depend on iterative execution. With the Nornir runtime system for parallel programs, which is a Kahn Process Network implementation, we addressed and solved several of these limitations. However, it is more difficult to use than other frameworks due to its complex programming model. In this paper, we build on the knowledge gained from Nornir and present a new framework, called P2G, designed specifically for developing and processing distributed real-time multimedia data. P2G supports arbitrarily complex dependency graphs with cycles, branches and deadlines, and provides both data- and task-parallelism. the framework is implemented to scale transparently with available (heterogeneous) resources, a concept familiar from the cloud computing paradigm. We have implemented an (interchangeable) P2G kernel language to ease development. In this paper, we present a proof of concept implementation of a P2G execution node and some experimental examples using complex workloads like Motion JPEG and K-means clustering. the results show that the P2G system is a feasible approach to multimedia proce

关键词： Kernel Multimedia communication parallel processing Runtime Streaming media Batch production systems Pipelines

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Optimizing multicore performance with message driven execution: A case study

Optimizing multicore performance with message driven executi...

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international conference on High Performance Computing

作者： Pritish Jetley Laxmikant V. Kale Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

With the growing amount of parallelism available on today's multicore processors, achieving good performance at scale is challenging. We approach this issue through an alternative to traditional thread-based paradigms for writing shared memory programs, namely message driven multicore programming. We study a number of optimizations that improve the efficiency of message driven programs on multicore architectures. In particular, we focus on the following runtime system-enabled optimizations: (i) grainsize control to effect a good concurrency-overhead tradeoff, (ii) dynamic balancing of processor load, (iii) low-overhead, asynchronous communication for lock-free and message-driven execution and (iv) communication-reduction through a novel chunked shared array abstraction. the practical impact of these optimizations is quantified through a parallel kd-tree construction program written in the message-driven paradigm. A comparison of the optimized code with a state-of-the-art parallel kd-tree construction program is also presented.

关键词： Multicore processing Program processors Runtime Optimization Arrays Partitioning algorithms Message systems

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Building High-Performance Application Protocol Parsers on Multi-core architectures

Building High-Performance Application Protocol Parsers on Mu...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Kai Zhang Junchang Wang Bei Hua Xinan Tang School of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

Parsing packet payloads according to the syntax and semantics of an application protocol is a key step in analyzing network traffic. However, it is still a challenge to fulfill this task with high speed(10Gbps+) because parsing packets through deep-content analysis to build a corresponding syntax tree requires tremendous computing resources. Multi-core architectures provide a viable solution for building high-performance parsers for application protocols. Existing sequential application protocol parsers are hard to be reused, and building a new protocol parser from scratch is error-prone and time-consuming. this paper proposes a general and efficient approach to building high-performance parallel application protocol parsers on multi-core platforms. First, the open-source lexical analyzer FLEX is used to describe a protocol and generate a sequential parser. then a source-to-source translation is performed to transform the sequential parser into a parallel one. Finally, an efficient parallel run-time system is built by employing lock-free design principles from top to bottom to support multi-threaded execution on multi-core processors. Experimental results show that our parsers achieve nearly 20Gbps for average HTTP packets and 5Gbps for the challenging smaller FIX packets.

关键词： Protocols Pipelines Flexible printed circuits Multicore processing Buildings Servers

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Real-Time Scan Conversion for Ultrasound Imaging Based on CUDA with Direct3D Display

Real-Time Scan Conversion for Ultrasound Imaging Based on CU...

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international conference on Bioinformatics and Biomedical Engineering (ICBBE)

作者： Li Wang Dan Shi Anyuan Zhao Chaowei Tan Dong C. Liu Computer Science College Sichuan University Chengdu China

Ultrasonic scan conversion (SC) is one of the most important and widely-used technology in Medical Ultrasound Imaging. However, real-time processing of SC is computationally intensive, involving in calculation of inverse tangents, square roots to determine the scanning angle and depth of a beam followed by interpolation both in axial and lateral directions. In this paper, a very efficient implementation of ultrasonic scan conversion on the Compute Unified Device Architecture (CUDA™) platform developed by NVIDIA® and using the interoperability of Direct3D (D3D) and CUDA to display is presented. By exploiting the implicit parallelism and reasonable performance optimization strategies based on the graphics hardware, this parallel scan conversion algorithm obtains a high speed up. It achieves a frame rate of about more than 746 fps with the picture size of 3121* 936, which is about 300 times faster than the CPU implementation.

关键词： Graphics processing unit Interpolation Ultrasonic imaging Pixel Instruction sets Memory management Imaging

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A new hardware architecture for H.264 intra prediction frame processing

A new hardware architecture for H.264 intra prediction frame...

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international conference on Internet Multimedia Services Architecture and Applications, IMSAA

作者： Xu Shou-Gen Wang Ming-Jiang Zuo Shi-Kai ShenZhen Graduate School Harbin Institute of Technology ShenZhen Guangdong China

this paper presents a hardware architecture for H.264 intra prediction frame processing. this design reuse some modules according to the common parts of luma 165;16 prediction and chroma 85;8 prediction in arc... 详细信息

this paper presents a hardware architecture for H.264 intra prediction frame processing. this design reuse some modules according to the common parts of luma 16×16 prediction and chroma 8×8 prediction in architecture and algorithm. thereby reduces the area of chip and cost, and enhances its market competition. the parallel pipeline is also adopted to enhance the encode efficiency. the top-down design method is adopted in this design. In the beginning the system architecture and C model are designed. then we implemented the architecture by Verilog HDL. After the ASIC synthesis, which is based on Chartered 0.13μm technology library, it can run 1080P@30 under the clock frequency 102M with 386.46K logic gates. the result of simulation and synthesis show that the timing and area requirement of design are both capable for 1080P@30fps HD applications.

关键词： Transforms Quantization Hardware Arrays Image reconstruction Streaming media

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Performance Evaluation of the Multi-Device OpenCL FDTD Solver

Performance Evaluation of the Multi-Device OpenCL FDTD Solve...

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European conference on Antennas and Propagation

作者： Tomasz P. Stefanski Nicolas Chavannes Niels Kuster IT'IS Foundation SPEAG Software R&D

ISBN: (纸本)9781457702501

We present results of an evaluation of a multi-device OpenCL FDTD solver. Portability between hardware manufactured by different vendors and also between highly specialized and parallel computing architectures available on the market, i.e. GPUs, multi-core CPUs and devices integrating both technologies in a single-die IC, is the main advantage of this solver. For code execution on GPUs, the computational domain is decomposed along the slowest direction, and electromagnetic field boundary data is shared between neighboring subdomains. the communication overhead between GPUs is proportional to the area of the boundary and represents the rate-limiting step of the method. Utilized hardware devices allow the communication overhead to be hidden by computations for sufficiently large simulation domains, giving a scaling efficiency higher than 90%. CPUs placed in different sockets on a motherboard are visible by the OpenCL driver as a single computing device with an aggregated number of cores, thus decomposition of the domain is not necessary for solver execution on multi-core CPUs. the paper subsequently shows results of numerical tests aimed at evaluation of the developed code in realistic simulations of problems in computational electromagnetics.

关键词： Graphics processing unit Computational modeling Finite difference methods Time domain analysis Runtime Instruction sets Hardware

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