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Building High-Performance Application Protocol Parsers on Multi-core architectures

Building High-Performance Application Protocol Parsers on Mu...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Kai Zhang Junchang Wang Bei Hua Xinan Tang School of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

Parsing packet payloads according to the syntax and semantics of an application protocol is a key step in analyzing network traffic. However, it is still a challenge to fulfill this task with high speed(10Gbps+) because parsing packets through deep-content analysis to build a corresponding syntax tree requires tremendous computing resources. Multi-core architectures provide a viable solution for building high-performance parsers for application protocols. Existing sequential application protocol parsers are hard to be reused, and building a new protocol parser from scratch is error-prone and time-consuming. this paper proposes a general and efficient approach to building high-performance parallel application protocol parsers on multi-core platforms. First, the open-source lexical analyzer FLEX is used to describe a protocol and generate a sequential parser. then a source-to-source translation is performed to transform the sequential parser into a parallel one. Finally, an efficient parallel run-time system is built by employing lock-free design principles from top to bottom to support multi-threaded execution on multi-core processors. Experimental results show that our parsers achieve nearly 20Gbps for average HTTP packets and 5Gbps for the challenging smaller FIX packets.

关键词： Protocols Pipelines Flexible printed circuits Multicore processing Buildings Servers

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Real-Time Scan Conversion for Ultrasound Imaging Based on CUDA with Direct3D Display

Real-Time Scan Conversion for Ultrasound Imaging Based on CU...

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international conference on Bioinformatics and Biomedical Engineering (ICBBE)

作者： Li Wang Dan Shi Anyuan Zhao Chaowei Tan Dong C. Liu Computer Science College Sichuan University Chengdu China

Ultrasonic scan conversion (SC) is one of the most important and widely-used technology in Medical Ultrasound Imaging. However, real-time processing of SC is computationally intensive, involving in calculation of inverse tangents, square roots to determine the scanning angle and depth of a beam followed by interpolation both in axial and lateral directions. In this paper, a very efficient implementation of ultrasonic scan conversion on the Compute Unified Device Architecture (CUDA™) platform developed by NVIDIA® and using the interoperability of Direct3D (D3D) and CUDA to display is presented. By exploiting the implicit parallelism and reasonable performance optimization strategies based on the graphics hardware, this parallel scan conversion algorithm obtains a high speed up. It achieves a frame rate of about more than 746 fps with the picture size of 3121* 936, which is about 300 times faster than the CPU implementation.

关键词： Graphics processing unit Interpolation Ultrasonic imaging Pixel Instruction sets Memory management Imaging

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A new hardware architecture for H.264 intra prediction frame processing

A new hardware architecture for H.264 intra prediction frame...

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international conference on Internet Multimedia Services Architecture and Applications, IMSAA

作者： Xu Shou-Gen Wang Ming-Jiang Zuo Shi-Kai ShenZhen Graduate School Harbin Institute of Technology ShenZhen Guangdong China

this paper presents a hardware architecture for H.264 intra prediction frame processing. this design reuse some modules according to the common parts of luma 165;16 prediction and chroma 85;8 prediction in arc... 详细信息

this paper presents a hardware architecture for H.264 intra prediction frame processing. this design reuse some modules according to the common parts of luma 16×16 prediction and chroma 8×8 prediction in architecture and algorithm. thereby reduces the area of chip and cost, and enhances its market competition. the parallel pipeline is also adopted to enhance the encode efficiency. the top-down design method is adopted in this design. In the beginning the system architecture and C model are designed. then we implemented the architecture by Verilog HDL. After the ASIC synthesis, which is based on Chartered 0.13μm technology library, it can run 1080P@30 under the clock frequency 102M with 386.46K logic gates. the result of simulation and synthesis show that the timing and area requirement of design are both capable for 1080P@30fps HD applications.

关键词： Transforms Quantization Hardware Arrays Image reconstruction Streaming media

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Performance Evaluation of the Multi-Device OpenCL FDTD Solver

Performance Evaluation of the Multi-Device OpenCL FDTD Solve...

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European conference on Antennas and Propagation

作者： Tomasz P. Stefanski Nicolas Chavannes Niels Kuster IT'IS Foundation SPEAG Software R&D

ISBN: (纸本)9781457702501

We present results of an evaluation of a multi-device OpenCL FDTD solver. Portability between hardware manufactured by different vendors and also between highly specialized and parallel computing architectures available on the market, i.e. GPUs, multi-core CPUs and devices integrating both technologies in a single-die IC, is the main advantage of this solver. For code execution on GPUs, the computational domain is decomposed along the slowest direction, and electromagnetic field boundary data is shared between neighboring subdomains. the communication overhead between GPUs is proportional to the area of the boundary and represents the rate-limiting step of the method. Utilized hardware devices allow the communication overhead to be hidden by computations for sufficiently large simulation domains, giving a scaling efficiency higher than 90%. CPUs placed in different sockets on a motherboard are visible by the OpenCL driver as a single computing device with an aggregated number of cores, thus decomposition of the domain is not necessary for solver execution on multi-core CPUs. the paper subsequently shows results of numerical tests aimed at evaluation of the developed code in realistic simulations of problems in computational electromagnetics.

关键词： Graphics processing unit Computational modeling Finite difference methods Time domain analysis Runtime Instruction sets Hardware

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Dynamic thread Partition Algorithm Based on Sharing Data on CMP

Dynamic Thread Partition Algorithm Based on Sharing Data on ...

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IEEE international conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Deng Zhou Ye Tian Hong Shen School of Computer Science University of Science and Technology of China China School of Computer Science University of Adelaide Australia

At the level of multi-core processors that share the same cache, data sharing among threads which belong to different cores may not enjoy the benifit of non-uniform cache access because it is difficult to determine which core should be set as the local position of data block while each cache block is setting as one of the core's local block. Studies have found that the cost of long latency access can be reduced by using a proper thread partition/allocation algorithm [5]. However, at present work, researchers pay little attention to thread partitioning algorithms which can reduce the cost of long latency access. In this paper, we present a dynamic thread partitioning algorithm according to data sharing among threads at the level of cache-shared-multicore processers. In our design, the algorithm makes the best effort to minimize shared block accessed by threads of different cores. Compared with the existing work, our new algorithm achieves a performance improvement. We perform experiments on 4 cores and more than 100 threads and the result show that our algorithm can reduce the interaction of threads belonging to different cores between 30% and 50% over the previously known solutions.

关键词： Partitioning algorithms Clustering algorithms Algorithm design and analysis Instruction sets Heuristic algorithms Arrays Multicore processing

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Balanced minimal latency RNS addition for moduli set {2n −1, 2n, 2n +1}

Balanced minimal latency RNS addition for moduli set {2n −1...

引用

international conference on Systems, Signals and Image processing, IWSSIP

作者： Ghassem Jaberipur Saeed Nejati Department of Electrical and Computer Engineering Shahid Beheshti University Tehran Iran

the classical RNS moduli set RNS C = {2 n -1, 2 n , 2 n +1} is widely used in digital signal/image processing and generally in computer arithmetic with residue number systems (RNS). this popularity is due to possibility of efficient binary to/from RNS conversions and existence of modulo-(2 n ± 1) adder architectures that are quite competitive with ordinary modulo-2 n adders. For example, there are modulo-(2 n -1) and -2 n parallel prefix adders with the minimal latency of (3 + 2[log n]) unit gate delay (UGD), while latencies of the fastest existing modulo-(2 n + 1) adders are 1, 2 or 3 UGDs more, depending on the encoding of residues. In particular diminished-1 (D1) representation of residues, in one design, has led to the least latency of (4 + 2[log n]) UGDs. Given that RNS C addition is undertaken in three parallel computation channels corresponding to the three moduli, it is desirable to device a (3 + 2[log n])-UGD modulo-(2 n + 1) adder as well. therefore, we are motivated to improve the performance of the aforementioned least-latency D1 design. To achieve this goal in this paper, we use some of the existing techniques for zero handling associated with D1 representation. Our UGD measures are supported by the synthesis results, except for less than 5% deviation due to reasonably expected interconnection and routing effects.

关键词： Adders Delay Encoding Logic gates Digital signal processing Complexity theory Dynamic range

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Solving Motion Law by Numerical Simulation on Bowl Seeding Transplanting Robot

Solving Motion Law by Numerical Simulation on Bowl Seeding T...

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Computer and Computing Technologies in Agriculture V——5th IFIP TC 5/SIG 5.1 conference(CCTA 2011) Part Ⅲ

作者： Chunhui Qi Jianping Hu Jun Ma Jianbing Zhang Key Laboratory of Modern Agricultural Equipment and Technology Ministry of Education & Jiangsu ProvinceJiangsu UniversityHigh-tech Key Laboratory of Agricultural Equipment & Intelligentization of Jiangsu Province

ISBN: (纸本)9783642272745

the paper using the inverse kinematics theory of the parallel mechanism,studied the movable needs of the transplanting *** the inverse kinematics formula of transplanting *** the demand of the "fetch and plant" operations,made an important research on the two trajectory planning methods of the moving platform:quintic and septic polynomial motion laws,acquired their variation rules of displacement,velocity,acceleration and saltus by using matlab software,and to make *** selected the law of motion equation,through numerical simulation of inverse kinematics by matlab,acquired kinematic parameters angular speed and acceleration of the two active motors,can be used as the priority basis for control the movement of the manipulator.

关键词： parallel mechanism transplanting bowl seeding trajectory planning inverse position numerical simulation

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Distributed event processing for activity recognition 11

Distributed event processing for activity recognition

引用

Proceedings of the 5th ACM international conference on Distributed event-based system

作者： Visalakshmi Suresh Paul Ezhilchelvan Paul Watson Cuong Pham Dan Jackson Patrick Olivier Newcastle University Newcastle Upon Tyne United Kingdom Newcastle University Newcastle upon tyne United Kingdom

ISBN: (纸本)9781450304238

Stream-processing systems inevitably face unpredictable variations in incoming event loads. One way of handling this without affecting end-to-end performance metrics, will be to dynamically distribute event-processing on multiple computers and thus avail compute power for optimal performance. More precisely, data streams are processed in part or in parallel on multiple computers connected by a high bandwidth network. the number of computers being used is to be varied dynamically to cope with input load fluctuations. this paper uses data from ambient kitchen to make a preliminary assessment of performance advantages by distribution of real-time data stream processing. the motivation is to leverage cloud computing for optimal realtime event processing.

关键词： real time and embedded systems distributed applications performance attributes

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A Naive-Bayesian Methodology to Classify Echo Cardiographic Images through SQL

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5th international conference on Knowledge, Information, and Creativity Support Systems

作者： Nandagopalan, S. Adiga, B. S. Sudarshan, T. S. B. Dhanalakshmi, C. Manjunath, C. N. Amrita Sch Engn Dept Comp Sci Si Engn Amrita Vishwa Vidyapeetham Bangalore Karnataka India Tata Consult Serv Parallel Comp Div Bangalore Karnataka India Amrita Sch Engn Dept Comp Sci & Engn Amrita Vishwa Vidyapeetham Bangalore Karnataka India Sri Jayadeva Inst Cardiovasc Sci & Res Dept Echocardiog Bangalore Karnataka India Sri Jayadeva Inst Cardiovasc Sci & Res Bangalore Karnataka India

ISBN: (纸本)9783642247873

Generally patient data in healthcare environments exist in relational databases. Classification of echocardiographic images is an important data mining task that helps hospitals without transferring the data in any form. this paper proposes a novel method to accomplish this task using naive Bayesian model via SQL. the proposed method has two phases. the first phase builds a knowledge base using many normal and abnormal subjects and the second phase uses this knowledge to categorize an unseen subject into appropriate class. the image features such as cardiac chamber dimensions (specifically Left Ventricle - LV), Ejection Fraction, Mitral valve (MV) orifice area, etc., are computed by first segmenting the image by employing advanced image processing techniques. For instance, to segment echo images we employ an efficient SQL based Fast K-Means algorithm combined with a greedy active contour algorithm for accurate boundary detection. Additional features such as textural, statistical, and histogram are computed and added to the classifier model by analyzing color Doppler echo images to strengthen the classifier accuracy. Our SQL based naive Bayesian classifier model is built with 7 schema, simple yet efficient SQL queries and thus providing an accurate classification of patients as normal or abnormal. the model is trained with 112 patient data and we believe that the clinical decision is simplified and can happen on-the-fly. Experimental results presented in this paper show an increased accuracy of 87.48% against the other state-of-the art segmentation and classification methods reported.

关键词： Echocardiographic image Naive-Bayseian Classification K-Means Segmentation SQL Active Contour

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Optimizing Web Browser on Many-Core architectures

Optimizing Web Browser on Many-Core Architectures

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IEEE international conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Lingjun Fan Weisong Shi Shibin Tang Chenggang Yan Dongrui Fan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Wayne State University Detroit USA

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. this leads to more and more performance requirements of a Web browser, for which user experience is very important. this situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.

关键词： Browsers HTML Web pages Layout Multicore processing System-on-a-chip

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