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Automated Tuning in parallel Sorting on Multi-core architectures

Automated Tuning in Parallel Sorting on Multi-core Architect...

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16th international Euro-Par conference on parallel processing

作者： Lin, Haibo Li, Chao Wang, Qian Zhao, Yi Pan, Ninghe Zhuang, Xiaotong Shao, Ling IBM Res Beijing Beijing Peoples R China Univ Massachusetts Boston MA USA Beijing Inst Technol Beijing Peoples R China IBM Syst & Technol Grp Beijing Peoples R China IBM Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9783642152764

Empirical search is an emerging strategy used in systems like ATLAS, FFTW and SPIRAL to find the parameter values of the implementation that deliver near-optimal performance for a particular machine. However, this approach has only proven successful for scientific kernels or serial symbolic sorting. Even commercial libraries like Intel MKL or IBM ESSL do not include parallel version of sorting routines. In this paper we study empirical search in the generation of parallel sorting routines for multi-core systems. parallel sorting presents new challenges that the relative performance of the algorithms depends not only on the characteristics of the architectures and input data, but also on the data partitioning schemes and thread interactions. We have studied parallel sorting algorithms including quick sort, cache-conscious radix sort, multi-way merge sort, sample sort and quick-radix sort, and have built a sorting library using empirical search and artificial neural network. Our results show that this sorting library could generate the best parallel sorting algorithms for different input sets on both x86 and SPARC multi-core architectures, with a peak speedup of 2.2x and 3.9x, respectively.

关键词： Sorting

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A New parallel Method of Smith-Waterman Algorithm on a Heterogeneous Platform

A New Parallel Method of Smith-Waterman Algorithm on a Heter...

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10th international conference on algorithms and architectures for parallel processing

作者： Chen, Bo Xu, Yun Yang, Jiaoyun Jiang, Haitao Univ Sci & Technol China Dept Comp Sci Key Lab High Performance Comp Hefei Anhui Peoples R China

ISBN: (纸本)9783642131189

Smith-Waterman algorithm is a classic dynamic programming algorithm to solve the problem of biological sequence alignment. However, with the rapid increment of the number of DNA and protein sequences, the originally sequential algorithm is very time consuming due to there existing the same computing task computed repeatedly on large-scale data. Today's CPU (graphics processor unit) consists of hundreds of processors, so it has a more powerful computation capacity than the current multicore CPU. And as the programmability of GPU improved continuously, using it to do generous purpose computing is becoming very popular. In order to accelerate sequence alignment, previous researchers use the parallelism of the anti-diagonal of similarity matrix to parallelize the Smith-Waterman algorithm on CPU. In this paper, we design a new parallel algorithm which exploits the parallelism of the column of similarity matrix to parallelize the Smith-Waterman algorithm on a heterogeneous system based on CPU and CPU. the experiment result shows that our new parallel algorithm is more efficient than that of previous, which takes full advantage of the features of both the CPU and CPU and obtains approximately 37 times speedup compared with the sequential algorithm named OSEARCH implemented on Intel dual-core E2140 processor.

关键词： parallel algorithms

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Query Optimization over parallel Relational Data Warehouses in Distributed Environments by Simultaneous Fragmentation and Allocation

Query Optimization over Parallel Relational Data Warehouses ...

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10th international conference on algorithms and architectures for parallel processing

作者： Bellatreche, Ladjel Cuzzocrea, Alfredo Benkrid, Soumia Univ Poitiers LISI ENSMA Futuroscope France Univ Calabria ICAR CNR Cosenza Italy ESI Natl High Sch Comp Sci Algiers Algeria

ISBN: (纸本)9783642131189

parallel database technology has already shown its efficiency in supporting high-performance Online Analytical processing (OLAP) applications. this scenario implies achieving query optimization over relational Data Warehouses (RDW) on top of which typical OLAP functionalities, such as roll-up, drill-down and aggregate query answering, can be implemented. As a result, it follows the emerging need for a comprehensive methodology able to support the design of RDW over parallel and distributed environments in all the phases, including data partitioning, fragment allocation, and data replication. Existing design approaches have an important limitation: fragmentation and allocation phases are performed in an isolated manner. In order to overcome this limitation, in this paper we propose a new methodology for designing parallel RDW over distributed environments, for query optimization purposes. the methodology is illustrated on database clusters, as a noticeable case of distributed environments. Contrary to state-of-the-art approaches where allocation is performed after fragmentation, in our approach we propose allocating fragments just during the partitioning phase. Also, a naive replication algorithm that takes into account the heterogeneous characteristics of our reference architecture is proposed.

关键词： Data warehouses

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SV: Enhancing SIMD architectures via Combined SIMD-Vector Approach

SV: Enhancing SIMD Architectures via Combined SIMD-Vector Ap...

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10th international conference on algorithms and architectures for parallel processing

作者： Huang, Libo Wang, Zhiying Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9783642131189

SIMD architectures are ubiquitous in general purpose and embedded processors to achieve future multimedia performance goals. However, limited to on chip resources and off-chip memory bandwidth, current SIMD extension only works on short sets of SIMD elements. this leads to large parallelization overhead for small loops in multimedia applications such as loop handling and address generation. this paper presents SIMD-Vector (SV) architecture to enhance SIMD parallelism exploration. It attempts to gain the benefits of both SIMD instructions and more traditional vector instructions which work on numerous values. Several instructions are extended that allows the programmer to work on large vectors of data and those large vectors are executed on a smaller SIMD hardware by a loop controller. To preserve the register file size for holding much longer vectors, we introduce a technique that the long vector references are performed on only one SIMD register in many iterations. We provide a detailed description of the SV architecture and its comparison with traditional vector architecture. We also present a quantitative analysis of the dynamic instruction size decrease and performance improvement of SV architecture.

关键词： SIMD vector performance loop

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parallel batch B+-tree insertion on multi-core architectures

Parallel batch B+-tree insertion on multi-core architectures

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5th international conference on Frontier of Computer Science and Technology, FCST 2010

作者： Liao, Jiangmiao Chen, Hu Yuan, Yixia Jianqing, X.I. School of Software Engineering South China University of Technology Guangzhou China School of Computer Science and Engineering South China University of Technology Guangzhou China

ISBN: (纸本)9780769541396

Multi-core computers have become more and more popular, which presents new opportunities for improving performance of database systems. How to exploit the potential performance on multi-core systems has become a key figure now. In database systems, B+-tree is the most widely-used index structure for speeding up performance of database systems. this paper implements the algorithm of parallel batch B+-tree insertion with multithreaded disk buffer. In our parallel batch B+-tree insertion algorithm (PBI), records can be inserted into index file concurrently by different threads. the key of the algorithm is to make traditional insertion into batch insertion. Our experimental results show that our system achieves a higher performance on multi-core systems. © 2010 IEEE.

关键词： Database systems

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A parallel programming framework for multi-core DNA sequence alignment

A parallel programming framework for multi-core DNA sequence...

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4th international conference on Complex, Intelligent and Software Intensive Systems (CICIS)

作者： Almeida, Tiago Roma, Nuno Univ Tecn Lisboa IST INESC ID Lisbon Portugal

ISBN: (纸本)9780769539676

A new parallel programming framework for DNA sequence alignment in homogeneous multi-core processor architectures is proposed. Contrasting with traditional coarse-grained parallel approaches, that divide the considered database in several smaller subsets of complete sequences to be aligned with the query sequence, the presented methodology is based on a slicing procedure of both the query and the database sequence under consideration in several tiles/chunks that are concurrently processed by the several cores available in the multi-core processor. the obtained experimental results have proven that significant accelerations of traditional biological sequence alignment algorithms can be obtained, reaching a speedup that is linear with the number of available processing cores and very close to the theoretical maximum.

关键词： Multi-core processor parallel programming Computational biology framework

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Automatically Tuning Sparse Matrix-Vector Multiplication for GPU architectures

Automatically Tuning Sparse Matrix-Vector Multiplication for...

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5th international conference on High Performance Embedded architectures and Compilers

作者： Monakov, Alexander Lokhmotov, Anton Avetisyan, Arutyun Inst Syst Programming RAS 25 Solzhenitsyna St Moscow 109004 Russia Imperial Coll London Dept Computat London SW7 2AZ England

ISBN: (纸本)9783642115141

Graphics processors are increasingly used in scientific applications due to their high computational power, which comes from hardware with multiple-level parallelism and memory hierarchy. Sparse matrix computations frequently arise in scientific applications, for example, when solving PDEs on unstructured grids. However, traditional sparse matrix algorithms are difficult to efficiently parallelize for GPUs due to irregular patterns of memory references. In this paper we present a new storage format for sparse matrices that better employs locality, has low memory footprint and enables automatic specialization for various matrices and future devices via parameter tuning. Experimental evaluation demonstrates significant speedups compared to previously published results.

关键词： Graphics processing unit

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

16th International Euro-Par Conference on Parallel Processin...

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

ISBN: (纸本)9783642152764

the proceedings contain 104 papers. the special focus in this conference is on parallel processing. the topics include: A parallel implementation of the Jacobi-Davidson eigensolver and its application in a plasma turbulence code;scheduling parallel eigenvalue computations in a quantum chemistry code;Scalable parallelization strategies to accelerate NuFFT data translation on multicores;multicore and Manycore Programming;javaSymphony: A programming and execution environment for parallel and distributed many-core architectures;scalable producer-consumer pools based on elimination-diffraction trees;productivity and performance: Improving consumability of hardware transactional memory through a real-world case study;exploiting fine-grained parallelism on cell processors;optimized on-chip-pipelined mergesort on the cell/B.E.;transactional mutex locks;Near-optimal placement of MPI processes on hierarchical NUMA architectures;parallel enumeration of shortest lattice vectors;A parallel GPU algorithm for mutual information based 3D nonrigid image registration;Multi-GPU and multi-CPU parallelization for interactive physics simulations;Long DNA sequence comparison on multicore architectures;adaptive fault tolerance for many-core based space-borne computing;Maestro: Data orchestration and tuning for openCL devices;multithreaded Geant4: Semi-automatic transformation into scalable thread-parallel software;parallel exact time series motif discovery;optimized dense matrix multiplication on a many-core architecture;exceptions for algorithmic skeletons;a language-based tuning mechanism for task and pipeline parallelism;A study of a software cache implementation of the OpenMP memory model for multicore and manycore architectures;Programming CUDA-based GPuS to simulate two-layer shallow water flows;theory and algorithms for parallel computation;analysis of multi-organization scheduling algorithms;Area-maximizing schedules for series-parallel DAGs;parallel Selection by Regular Sampling;a

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

16th International Euro-Par Conference on Parallel Processin...

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

ISBN: (纸本)9783642152900

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parallel implementation of 2D Daubechies - D4 transform in a cluster

Parallel implementation of 2D Daubechies - D4 transform in a...

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5th international conference on Computer Sciences and Convergence Information Technology, ICCIT 2010

作者： Ajdari, Jaumin Hoxha, Fatmir Faculty of Contemporary Science and Technologies South East European University Tetovo Macedonia Faculty of Natural Science Universiy of Tirana Albania

ISBN: (纸本)9788988678299

Wavelet transform is an important mathematical tool with strong application in signal processing. From the mathematical point of view many different wavelet transforms are developed, where orthogonal wavelet transforms are more important. Also, various algorithms for their computations are developed. In this paper we present the parallel implementation of the orthogonal wavelet transform named Daubechies D4 transform, which consists of four taps filters. At the beginning, a short mathematical introduction of the Daubechies D4 transform is presented. After that the sequential and parallel algorithm implementations are analyzed. A parallel implementation for the PC cluster environment is done. We have analyzed two ways of parallel implementation, one with row mapping and the other with block mapping (mesh architecture of the processing elements). For practical implementation the C++ programming language and MPI paradigm (for parallel environment) are used. Finally, the mathematical complexity of these implementations is presented. In particular, we have analyzed separately the complexity of computations and communications. It is shown, also, that the complexity is between O(log2n) and O(n2 / p). At the end, a comparison of sequential and parallel implementations is presented according to the results obtained by testing the practical implementations.

关键词： Mapping

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