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Analysis of scalability of parallel algorithms and architectures;a survey 91

Analysis of scalability of parallel algorithms and architect...

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5th ACM international conference on Supercomputing

作者： Kumar, Vipin Gupta, Anshul Department of Computer Science University of Minnesota Minneapolis MN

ISBN: (纸本)0897914341

the scalability of a parallel algorithm on a parallel architecture is a measure of its capability to effectively utilize an increasing number of processors. the scalability analysis may be used to select the best algorithm-architecture combination for a problem under different constraints on the growth of the problem size and the number of processors. It may be used to predict the performance of a parallel algorithm and a parallel architecture for a large number of processors from the known performance on fewer processors. For a fixed problem size it may be used to determine the optimal number of processors to be used and the maximum possible speedup for that problem size. the objective of this paper is to critically assess the state of the art in the theory of scalability analysis, and motivate further research on the development of new and more comprehensive analytical tools to study the scalability of parallel algorithms and architectures. We survey a number of techniques and formalisms that have been developed for studying the scalability issues, and discuss their interrelationships. © 1991 ACM.

关键词： Scalability

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5th international conference on parallel Computing Technologies, PaCT 1999

5th International Conference on Parallel Computing Technolog...

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5th international conference on parallel Computing Technologies, PaCT 1999

ISBN: (纸本)3540663630

the proceedings contain 59 papers. the special focus in this conference is on parallel Computing in Regular Structures. the topics include: Analytical modeling of parallel application in heterogeneous computing environments;skeletons and transformations in an integrated parallel programming environment;sequential unification and aggressive lookahead mechanisms for data memory accesses;a coordination model and facilities for efficient parallel computation;parallelizing of sequential programs on the basis of pipeline and speculative features of the operators;kinetic model of parallel data processing;PSA approach to population models for parallel genetic algorithms;highly accurate numerical methods for incompressible 3D fluid flows on parallel architectures;dynamic task scheduling with precedence constraints and communication delays;two-dimensional scheduling of algorithms with uniform dependencies;consistent lamport clocks for asynchronous groups with process crashes;comparative analysis of learning methods of cellular-neural associative memory;emergence and propagation of round autowave in cellular neural network;routing and embeddings in super cayley graphs;implementing cellular automata based models on parallel architectures;overview, design innovations, and preliminary results;implementing model checking and equivalence checking for time petri nets by the RT-MEC tool;learning concurrent programming;the speedup performance of an associative memory based logic simulator;a high-level programming environment for distributed memory architectures;virtual shared files;an object oriented environment to manage the parallelism of the FIIT applications;performance studies of shared-nothing parallel transaction processing systems;synergetic tool environments and logically instantaneous communication on top of distributed memory parallel machines.

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Improving the parallel Schnorr-Euchner LLL Algorithm

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Backes, Werner Wetzel, Susanne Stevens Inst Technol Hoboken NJ 07030 USA

ISBN: (纸本)9783642246494

this paper introduces a number of modifications that allow for significant improvements of parallel LLL reduction. Experiments show that these modifications result in an increase of the speed-up by a factor of more than 1.35 for SVP challenge type lattice bases in comparing the new algorithm with the state-of-the-art parallel LLL algorithm.

关键词： Computers

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A parallel data preprocessing algorithm for hierarchical clustering

A Parallel data preprocessing algorithm for hierarchical clu...

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5th international conference on Measuring Technology and Mechatronics Automation (ICMTMA)

作者： Li Zhao-Peng Li Zhao-jian Hunan Univ Humanities Sci & Technol Loudi 417000 Peoples R China

ISBN: (纸本)9780769549323;9781467356527

Hierarchical clustering technology plays a very important role in image processing, intrusion detection and bioinformatics applications, which is one of the most extensively studied branch in data mining. Presently the parallel hierarchical algorithms aren't very good at processing large data. To overcome this shortcomings, a new parallel data preprocessing algorithm based on Hierarchical Clustering is proposed in this paper this algorithm can reduce the scale of data and runtime. accounting for one tenth of it in the best situation. the experiment proof the performance of our algorithm.

关键词： hierarchical clustering parallel algorithms data preprocessing

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Design of an optical content-addressable parallel processor with applications to fast searching and information retrieval 5

Design of an optical content-addressable parallel processor ...

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5th international parallel processing Symposium, IPPS 1991

作者： Louri, Ahmed Department of Electrical and Computer Engineering University of Arizona TucsonAZ85721 United States

ISBN: (纸本)0818691670

Associative processing based on content-addressable memories has been argued to be the natural solution for non-numerical information processing applications. Unfortunately, the implementation requirements of these architectures using conventional electronic technology have been very cost prohibitive, and therefore associative processors have not been realized. Optics has the capability over electronics for directly supporting associative processing by providing economic and efficient interconnects, massive parallelism, and high-speed processing. this paper presents the principles of designing an optical content-addressable parallel processor called OCAPP, for the efficient support of parallel symbolic computing. the architecture is designed to fully exploit optics advantages in interconnects and high-speed operations, and is potentially very suitable for applications where the number of data sets to be operated on is high. Several search and retrieval algorithms are mapped onto OCAPP to illustrate its ability to support parallel symbolic computing. © 1991 IEEE.

关键词： Associative processing

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TRACKING OF SPACE OBJECTS USING MASSIVELY-parallel processing

TRACKING OF SPACE OBJECTS USING MASSIVELY-PARALLEL PROCESSIN...

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5th CONF ON SIGNAL AND DATA processing OF SMALL TARGETS

作者： MARSH, RA RUDD, JG thOMAS, SG IBM Federal Systems Co. (United Kingdom) IBM Federal Systems Co. (United States)

ISBN: (纸本)0819411906

the space track catalog of satellites in orbit is generally maintained using analytic methods. New technology developments in the area of parallel processing provide the capability to apply more exact methods to determine and maintain the ephemerides of a larger number of space objects more precisely. Space object tracking accuracy is becoming increasingly important in space programs such as the Space Station, where the collision hazard is critical, and for military application requiring precise positioning of satellites. Affordable massively parallel processing architectures will soon be available to address this problem. We expect that before long the number of processing elements in a single affordable box will approach or exceed the number of satellites in orbit. In this paper we consider algorithms and architectures for processing a large number of space objects in a parallel sense. these improvements will enable the tracking of many small objects with precision and will improve the confidence with which collision hazards can be assessed. In addition, as sensor capabilities are improved through technology upgrades, the accuracy of these computational methods will continue to exceed the precision of the measurements.

关键词： Satellites parallel processing Surface plasmons Collision avoidance Space operations Sensors Defense technologies Detection and tracking algorithms Precision measurement

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Research and Implementation of High Performance Traffic processing based on Intel DPDK 9

Research and Implementation of High Performance Traffic Proc...

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9th international conference on parallel architectures, algorithms and Programming (PAAP)

作者： Zhu, Wenjun Li, Peng Luo, Baozhou Xu, He Zhang, Yujie Nanjing Univ Posts & Telecommun Sch Comp Sci Nanjing 210003 Jiangsu Peoples R China Nanjing Univ Posts & Telecommun Sch Comp Sci Jiangsu High Technol Res Key Lab Wireless Sensor Nanjing 210003 Jiangsu Peoples R China

ISBN: (纸本)9781538694039

With the rapid development of Internet and the continuous rise of network users, the network traffic in various regions is increasing rapidly. In the face of a large number of high speed and high throughput of the network environment, traditional packet capture methods and processing capabilities cannot reach the corresponding speed, which results in severe packet loss. this paper focuses on a high-performance packet acquisition and distribution method to break through the performance bottleneck of universal servers and network cards. this paper studies a packet capture method based on DPDK platform, and uses the processing of hash value in RSS to improve the efficiency of data packet distribution, which realizes the process from performance acquisition to efficiently multi-core parallel processing. this method can effectively reduce packet loss and improve the data packet processing rate. It can also reduce resource waste and network overhead for traffic capture and distribution. Preliminary experiments show that DPDK-based traffic processing has obvious advantages over PF-RING and Netmap in data processing speed.

关键词： DPDK Traffic processing Distribution Multi-core parallel processing

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Numerical linear algebra on emerging architectures: the PLASMA and MAGMA projects

Numerical linear algebra on emerging architectures: the PLAS...

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5th Annual conference of Scientific Discovery through Advanced Computing (SciDAC 2009)

作者： Agullo, Emmanuel Demmel, Jim Dongarra, Jack Hadri, Bilel Kurzak, Jakub Langou, Julien Ltaief, Hatem Luszczek, Piotr Tomov, Stanimire Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA

the emergence and continuing use of multi-core architectures and graphics processing units require changes in the existing software and sometimes even a redesign of the established algorithms in order to take advantage of now prevailing parallelism. parallel Linear Algebra for Scalable Multi-core architectures (PLASMA) and Matrix Algebra on GPU and Multics architectures (MAGMA) are two projects that aims to achieve high performance and portability across a wide range of multi-core architectures and hybrid systems respectively. We present in this document a comparative study of PLASMA's performance against established linear algebra packages and some preliminary results of MAGMA on hybrid multi-core and GPU systems.

关键词： Graphics processing unit

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A parallel Distributed Algorithm for the Permutation Flow Shop Scheduling Problem

A Parallel Distributed Algorithm for the Permutation Flow Sh...

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10th international conference on algorithms and architectures for parallel processing

作者： Kouki, Samia Ladhari, Talel Jemni, Mohamed Ecole Super Sci & Tech Tunis Res Lab UTIC Tunis Tunisia Ecole Super Sci Econ & Commerce Tunis Tunisia

ISBN: (纸本)9783642131356

this paper describes a new parallel Branch-and-Bound algorithm for solving the classical permutation flow shop scheduling problem as well as its implementation on a cluster of six computers. the experimental study of our distributed parallel algorithm gives promising results and shows clearly the benefit of the parallel paradigm to solve large-scale instances in moderate CPU time.

关键词： Clustering algorithms

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Digit pipelined arithmetic for 3-D massively parallel optoelectronic circuits 5

Digit pipelined arithmetic for 3-D massively parallel optoel...

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5th international conference on Massively parallel processing

作者： Fey, D Degenkolb, M Scheuermann, C Erhard, W Friedrich Schiller Univ Inst Informat D-07743 Jena Germany

ISBN: (纸本)0818685727

A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit's core as smart pixel detector chip is presented. this architecture is well-suited for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. this allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. this is demonstrated for a pipelined arithmetic unit using a redundant number representation. A gate layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technolgy.

关键词： Timing circuits

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