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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3299 条记录，以下是2001-2010 订阅

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HPPC 2009: 3rd Workshop on Highly parallel processing on a Chip

HPPC 2009: 3rd Workshop on Highly Parallel Processing on a C...

引用

15th international Euro-Par conference on parallel Computing

作者： Forsell, Martti Traeff, Jesper Larsson VTT Tech Res Ctr Finland Oulu Finland NEC Europe Ltd NEC Labs Europe St Augustin Germany

ISBN: (纸本)9783642141218

To counter the relative decline in traditional, single-processor performance, architectures with significant on-chip parallelism for special and general-purpose computation have been marketed in the past few years with various degrees of success. Although the shift toward (general-purpose) parallel processing is inevitable and generally accepted, the road to travel is still essentially unclear - perhaps even unknown, as witnessed by the many different architectural proposals and products by both large and smaller vendors, the usual hype, as well as research projects in many different directions. © 2010 Springer-Verlag.

关键词： Industrial research

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Approximation for preemptive scheduling stochastic jobs on identical parallel machines

Approximation for preemptive scheduling stochastic jobs on i...

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2010 IEEE 5th international conference on Bio-Inspired Computing: theories and Applications, BIC-TA 2010

作者： Tang, Xiaoyong Li, Kenli Wu, Fan School of Computer and Communication Hunan University Changsha 410082 China

ISBN: (纸本)9781424464388

In this paper, the stochastic scheduling problem of minimizing the total weighted completion time on preemptive identical parallel machines is investigated. Each job has a processing time, which is a random variable and just given their distribution function. First, we extend the stochastic single-machine preemptive WSEPT rule to a multi-machine list scheduling policy, which we call P-WSEPT. then, we use LP based policy to analysis the performance guarantee of preemptive stochastic scheduling with release dates. © 2010 IEEE.

关键词： Distribution functions

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Adaptive scheduling for staged applications: the case of multiple processing units

Adaptive scheduling for staged applications: The case of mul...

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5th international conference on Internet and Web Applications and Services, ICIW 2010

作者： Al-Hakeem, Mohammad Shadi Heiß, Hans-Ulrich Communications and Operating Systems Group Berlin University of Technology Sekretariat EN6 Einsteinufer 17 10587 Berlin Germany

ISBN: (纸本)9780769540221

Staged design has been introduced as a programming paradigm to implement high performance Internet services that avoids the pitfalls related to conventional concurrency models. However, this design presents challenges concerning resource allocation to the individual stages, which have different demands that change during execution. On the other hand, processing resources have been shown to form the bottleneck in a variety of Internet-based applications. For this reason, parallel processing hardware techniques have been employed in order to cope with the massive concurrency and the increasing demands for performance aspects in these applications. Recently, the rise of multi-core technology introduces a hierarchic parallelism in modern server machines that has to be considered when allocating processing units in order to improve the utilization of these resources. this paper, introduces an adaptive policy to allocate processing units in Internet services that are based on the staged architecture. the proposed approach takes the hierarchic parallelism in account and adapts the resources assigned to the individual stages dynamically based on the observed demand of each stage using a feedback loop. Simulation results demonstrate that our approach achieves a competitive system throughput, avoids overhead that is associated with parallel processing, and successfully adapts resource allocation to dynamic changes in workload characteristics. © 2010 IEEE.

关键词： Resource allocation

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A GPU implementation for two MIMO-OFDM detectors

A GPU implementation for two MIMO-OFDM detectors

引用

2010 10th international conference on Embedded Computer Systems: architectures, Modeling and Simulation, IC-SAMOS 2010

作者： Nyländen, Teemu Janhunen, Janne Silvén, Olli Juntti, Markku Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781424479382

Two real-valued signal models based on selective spanning with fast enumeration (SSFE) and layered orthogonal lattice detector (LORD) algorithms are implemented on a Nvidia graphics processing unit (GPU). A 2 x 2 multiple-input multiple-output (MIMO) antenna system with 16-quadrature amplitude modulation (16-QAM) is assumed. the chosen level update vector for SSFE is based on computer simulation results carried out in MATLAB environment. We implemented the algorithms with Nvidia Quadro FX 1700 GPU and achieved a throughput of 36.06 Mbps for SSFE and 16.8 Mbps for LORD. the results show that the general-purpose graphics processing unit (GPGPU) has the potential to achieve high throughput, presuming a detection algorithm that allows efficient parallel processing. the latency of the control code and partial Euclidean distance (PED) calculations are very small-scale, but the latency of memory loads and stores to the GPUs global memory are significant. We also compare results from the trellis based detector implementation for GPU, where a more powerful GPU and a different detection algorithm are used. the GPUs offer superior computing power and programmability compared to the application specific software defined radio (SDR) designs implemented so far. ©2010 IEEE.

关键词： Graphics processing unit

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A comparison of pipelined parallel and iterative CORDIC design on FPGA

A comparison of pipelined parallel and iterative CORDIC desi...

引用

international conference on Industrial and Information Systems, ICIIS

作者： Ramesh Bhakthavatchalu M.S. Sinith Parvathi Nair K. Jismi Department of ECE Amrita Viswavidyapeetham University Kollam Kerala India Amrita Vishwa Vidyapeetham Coimbatore Tamil Nadu IN

Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. the paper compares the different CORDIC architectures with respect to their area, speed, and data throughput performance especially in three different major styles iterative, parallel and pipelined structures. All three designs were designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools.

关键词： Signal processing algorithms Hardware Algorithm design and analysis Clocks Mathematical model Computer architecture Field programmable gate arrays

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Using CPU stubs to optimize parallel processing tasks: An application of dynamic performance stubs

Using CPU stubs to optimize parallel processing tasks: An ap...

引用

international conference on Software Engineering Advances

作者： Trapp, Peter Meyer, Markus Facchi, Christian University of Applied Sciences Ingolstadt Ingolstadt Germany

ISBN: (纸本)9780769541440

Dynamic performance stubs provide a framework for the simulation of the performance behavior of software modules and functions. Hence, they can be used as an extension to software performance engineering methodologies. the methodology of dynamic performance stubs can be used for a gain oriented performance improvement. It is also possible to identify "hidden" bottlenecks and to prioritize optimization possibilities. Nowadays, the processing power of CPUs is mainly increasing by adding more cores to the architecture. To have benefits from this, new software is mostly designed for parallel processing, especially, in large software projects. As software performance optimizations can be difficult in these environments, new methodologies have to be defined. this paper extends and improves the methodology of CPU stubs and applies it to multi-core environments and parallel processing. the method is evaluated by means of a proof of concept. We were able to show that CPU stubs can be used to identify performance bottlenecks in parallel processing environments and to quantify the gain of different performance improvements. Hence, a new methodology for gain oriented optimization of CPU bound parallel processes has been validated in a casestudy. © 2010 IEEE.

关键词： Program processors

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Highly Scalable Multiprocessing algorithms for Preference-Based Database Retrieval

Highly Scalable Multiprocessing Algorithms for Preference-Ba...

引用

15th international conference on Database Systems for Advanced Applications

作者： Selke, Joachim Lofi, Christoph Balke, Wolf-Tilo Tech Univ Carolo Wilhelmina Braunschweig Inst Informat Syst Braunschweig Germany

ISBN: (纸本)9783642120978

Until recently algorithms continuously gained free performance improvements due to ever increasing processor speeds. Unfortunately, this development has reached its limit. Nowadays, new generations of CPUs focus on increasing the number of processing cores instead of simply increasing the performance of a single core. thus, sequential algorithms will be excluded from future technological advances. Instead, highly scalable parallel algorithms are needed to fully tap new hardware potentials. In this paper we establish a design space for parallel algorithms in the domain of personalized database retrieval, taking skyline algorithms as a representative example. We will investigate the spectrum of base operations of different retrieval algorithms and various parallelization techniques to develop a set of highly scalable and high-performing skyline algorithms for different retrieval scenarios. Finally, we extensively evaluate these algorithms to showcase their superior characteristics.

关键词： parallel algorithms

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Highly Scalable Text Mining - parallel Tagging Application

Highly Scalable Text Mining - Parallel Tagging Application

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5th international conference on Soft Computing, Computing with Words and Perceptions in System Analysis, Decision and Control

作者： Tekiner, Firat Tsuruoka, Yoshimasa Tsujii, Jun'ichi Ananiadou, Sophia UCLAN Sch Comp Engn & Phys Sci Preston PR1 2HE Lancs England Univ Manchester Nat Ctr Text Min Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9781424434299

there is an urgent need to develop new text mining solutions using High Performance Computing (HPC) and grid environments to tackle exponential growth in text data. Problem sizes are increasing by the day by addition of new text docments. the task of labelling sequence data such as part-of-speech (POS) tagging, chunking (shallow parsing) and named entity recognition is one of the most important tasks in Text Mining. Genia is a POS tagger which is specifically tuned for biomedical text. Genia is built with maximum entropy modelling and state of the art tagging algorithm. A parallel version of genia tagger application has been implemented and performance has been compared on a number of different architectures. the focus has been particularly on scalability of the application. Scaling of 512 processors has been achieved and a method to scale to 10000 processors is proposed for massively parallel Text Mining applications. the parallel implementation of genia tagger is done using MPI for achieving portable code.

关键词： HPC Text Mining Parsing parallel Computing

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P systems with shuffle operation

P systems with shuffle operation

引用

2010 IEEE 5th international conference on Bio-Inspired Computing: theories and Applications, BIC-TA 2010

作者： Niu, Yunyun Xu, Jinbang Subramaniant, K.G. Department of Control Science and Engineering Key Laboratory of Image Processing and Intelligent Control Huazhong University of Science and Technology 430074 Wuhan China School of Mathematical Sciences Universiti Sains Malaysia 11800 Penang Malaysia

ISBN: (纸本)9781424464388

Shuffle operation on trajectories is useful in modeling parallel composition of words and languages. In this work, a new class of P systems with shuffle operation is presented. Such a system has language-objects and shuffle-operation rules in its regions. It can be used as a language generator;specifically it is used to generate languages from sets of languages. Some comparison results are obtained, which show that the power of shuffle operation is enlarged in the framework of P systems. © 2010 IEEE.

关键词： Modeling languages

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parallel streaming intra prediction for full HD H.264 encoding

Parallel streaming intra prediction for full HD H.264 encodi...

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international conference on Embedded and Multimedia Computing

作者： Ren, Ju He, Yi Su, Huayou Wen, Mei Wu, Nan Zhang, Chunyuan Computer School National University of Defense Technology Changsha China

ISBN: (纸本)9781424477104

Intra prediction is the most important intensive computing component in H.264 intra frame coder. Its high computational costs give huge pressure to most current embedded programmable processors, especially in real-time HD H.264 video encoding. Stream processing model, an emerging parallel processing model supported by GPUs and most programmable processors, bridges the gap between flexible programmable processors and high-performance special-purpose processors. this paper presents parallel streaming intra prediction on programmable processors. Two methods of 7-steps block parallel and macro block parallel are designed to deal with the restrictions of parallel. Experiment results of full HD H.264 encoding show that our parallel streaming intra prediction methods accomplish obvious speedup (more than 5 times) on different programmable processors. Moreover, the entire streaming H.264 encoder with our parallel intra prediction method achieves real-time performance for encoding full HD H.264 video sequence. © 2010 IEEE.

关键词： Forecasting

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