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A parallel streaming motion estimation for real-time HD H.264 encoding on programmable processors

A parallel streaming motion estimation for real-time HD H.26...

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international conference on Frontier of Computer Science and Technology

作者： Ren, Ju Wen, Mei Zhang, Chunyuan Su, Huayou He, Yi Wu, Nan Computer School National University of Defense Technology China

ISBN: (纸本)9780769541396

Motion estimation is an important computing intensive component in most video compression standards. the high computational costs and heavy memory bandwidth requirements of motion estimation give huge pressure to most existing programmable processors, especially in real-time high definition H.264 video encoding. Emerging stream processing model supported by most programmable processors provide a powerful mechanism to achieve high performance in media processing, which brings an opportunity to relieve this pressure. this paper presents a parallel motion estimation algorithm based on stream processing. Many approaches are explored to enable high data reuse efficiency and computation parallelism for GPUs or other programmable processors. Experiment results of 1080p H.264 encoding show that our parallel streaming motion estimation applied on different programmable processors accomplishes obvious speedup (from1.8x to 8.1x) over the serial motion estimation. Furthermore, the results show that H.264 encoder achieves 30FPS performance which satisfies the real-time requirements of 1080p H.264/AVC. © 2010 IEEE.

关键词： Motion estimation

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Sparse matrix-vector multiplication based on network-on-chip in FPGA

Sparse matrix-vector multiplication based on network-on-chip...

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10th IEEE international conference on Computer and Information Technology, CIT-2010, 7th IEEE international conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Sun, Chi-Chia Götze, Jürgen Jheng, Hong-Yuan Ruan, Shanq-Jang Information Processing Lab Dortmund University of Technology Dortmund Germany Low-Power System Lab National Taiwan University of Science and Technology Taipei 106 Taiwan

ISBN: (纸本)9780769541082

A new method for performing Sparse Matrix-Vector Multiplication (SMVM) by using Network-on-Chip (NoC) architecture is described. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections or shared-buses. therefore, regular local data transfer is the major concern of many parallel implementations. However, when dealing with the parallel implementation of SMVM, which is the main step of all iterative algorithms for solving system of linear equations, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using a NoC architecture makes it possible to deal with arbitrary structure of the data transfers;i.e. with the irregular structure of the sparse matrices. So far, we have implemented the proposed SMVM calculator based on NoC architecture with the size of 4×4 and 5×5 in IEEE 754 single float point precision using FPGA. © 2010 IEEE.

关键词： Network-on-chip

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the High-Activity parallel Implementation of Data Preprocessing Based on MapReduce 1

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5th international conference on Rough Set and Knowledge Technology (RSKT)

作者： He, Qing Tan, Qing Ma, Xudong Shi, Zhongzhi Chinese Acad Sci Inst Comp Technol Key Lab Intelligent Informat Proc Beijing 100190 Peoples R China

ISBN: (数字)9783642162480

ISBN: (纸本)9783642162473

Data preprocessing is an important and basic technique for data mining and machine learning. Due to the dramatic increasing of information, traditional data preprocessing techniques are time-consuming and not fit for processing mass data. In order to tackle this problem, we present parallel data preprocessing techniques based on MapReduce which is a programming model to implement parallelization easily. this paper gives the implementation details of the techniques including data integration, data cleaning, data normalization and so on. the proposed parallel techniques can deal with large-scale data (up to terabytes) efficiently. Our experimental results show considerable speedup performances with an increasing number of processors.

关键词： Data preprocessing Speedup performance parallel computing Hadoop MapReduce

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Evaluation of parallel H.264 decoding strategies for the cell broadband engine 10

Evaluation of parallel H.264 decoding strategies for the cel...

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24th ACM international conference on Supercomputing, ICS'10

作者： Chi, Chi Ching Juurlink, Ben Meenderinck, Cor Technische Universität Berlin Franklinstrasse 28/29 10587 Berlin Germany Delft University of Technology Mekelweg 4 Delft Netherlands

ISBN: (纸本)9781450300186

How to develop efficient and scalable parallel applications is the key challenge for emerging many-core architectures. We investigate this question by implementing and comparing two parallel H.264 decoders on the Cell architecture. It is expected that future many-cores will use a Cell-like local store memory hierarchy, rather than a non-scalable shared memory. the two implemented parallel algorithms, the Task Pool (TP) and the novel Ring-Line (RL) approach, both exploit macroblock-level parallelism. the TP implementation follows the master-slave paradigm and is very dynamic so that in theory perfect load balancing can be achieved. the RL approach is distributed and more predictable in the sense that the mapping of macroblocks to processing elements is fixed. this allows to better exploit data locality, to overlap communication with computation, and to reduce communication and synchronization overhead. While TP is more scalable in theory, the actual scalability favors RL. Using 16 SPEs, RL obtains a scalability of 12x, while TP achieves only 10.3x. More importantly, the absolute performance of RL is much higher. Using 16 SPEs, RL achieves a throughput of 139.6 frames per second (fps) while TP achieves only 76.6 fps. A large part of the additional performance advantage is due to hiding the memory latency. From the results we conclude that in order to fully leverage the performance of future many-cores, a centralized master should be avoided and the mapping of tasks to cores should be predictable in order to be able to hide the memory latency. © 2010 ACM.

关键词： Cells

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Exploring Recognition Network Representations for Efficient Speech Inference on Highly parallel Platforms

Exploring Recognition Network Representations for Efficient ...

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11th Annual conference of the international-Speech-Communication-Association 2010

作者： Chong, Jike Gonina, Ekaterina You, Kisun Keutzer, Kurt Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA Parasians LLC Cape Charles VA USA Seoul Natl Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9781617821233

the emergence of highly parallel computing platforms is enabling new trade-offs in algorithm design for automatic speech recognition. It naturally motivates the following investigation: do the most computationally efficient sequential algorithms lead to the most computationally efficient parallel algorithms? In this paper we explore two contending recognition network representations for speech inference engines: the linear lexical model (LLM) and the weighted finite state transducer (WFST). We demonstrate that while an inference engine using the simpler LLM representation evaluates 22x more transitions per second than the advanced WFST representation, the simple structure of the LLM representation allows 4.7-6.4x faster evaluation and 53-65 x faster operands gathering for each state transition. We use the 5k Wall Street Journal corpus to experiment on the NVIDIA GTX480 (Fermi) and the NVIDIA GTX285 Graphics processing Units (GPUs), and illustrate that the performance of a speech inference engine based on the LLM representation is competitive with the WFST representation on highly parallel computing platforms.

关键词： Continuous Speech Recognition Data parallel Graphics processing Unit Linear Lexical Model Weighted Finite State Transducer

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Design and FPGA implementation of modular multiplication methods using cellular automata

Design and FPGA implementation of modular multiplication met...

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international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Z. Guitouni R. Chotin-Avot M. Machhout H. Mehrez R. Tourki Faculty of Sciences of Monastir Electronic and Micro Electronic Laboratory Tunisia LIP6/SOC Laboratory University of Paris VI France LIP6/S0C Laboratory University of Paris VI France

ISBN: (纸本)9781424463381;9781424463404

Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. they have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular automata over finite field GF(2 m ). Since they have regularity, modularity and concurrency, they are suitable for VLSI implementation. the proposed architectures can be easily implemented into the hardware design of crypto-coprocessors.

关键词： Field programmable gate arrays Computational modeling Concurrent computing Physics computing parallel processing Computer architecture Galois fields Very large scale integration Hardware Cryptography

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Performance Debugging of parallel Compression on Multicore Machines

Performance Debugging of Parallel Compression on Multicore M...

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8th international conference, PPAM 2009

作者： Borkowski, Janusz Polish Japanese Inst Informat Technol PL-02008 Warsaw Poland

ISBN: (纸本)9783642144028

the power of contemporary processors is based more and more on multicore architectures this kind of power is accessible only to parallel applications, which are able to provide work for each core. Creating a scalable parallel/multithreaded application efficiently using available cores is a difficult task, especially if I/O performance must be considered as well We consider a multithreaded database loader with a compressing function the performance of the loader is examined from a number of perspectives Because compression is a computationally intensive task, parallel execution can potentially provide a big advantage in this case A list or performance related areas we encountered is presented and discussed We identify and verify tools allowing us to deal with specific performance areas We find out, that only an orchestrated employment of several tools can bring the desired effect the discussion provides a general procedure one can follow when improving the performance of multithreaded programs Key performance areas specific to the database loader are pointed out A special interest, is directed towards performance variations observed when many parallel threads are active on it multicore CPU A significant slowdown of computations is observed if many threads are computing simultaneously the slowdown is related mainly to memory access and cache behavior and it is much larger for Core2 Quad system than a dual Xeon machine

关键词： Loaders

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Quasi-random Approach in the Grid Application SALUTE

Quasi-random Approach in the Grid Application SALUTE

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8th international conference, PPAM 2009

作者： Atanassov, Emanouil Karaivanova, Aneta Gurov, Todor Bulgarian Acad Sci Inst Parallel Proc BU-1113 Sofia Bulgaria

ISBN: (纸本)9783642144028

Stochastic algorithms for Ultra-fast Transport in sEmiconductors (SALUTE) is a Grid Application which integrates a set of novel Monte Gallo, quasi-Monte Carlo and hybrid algorithms for solving various computationally intensive problems important for industry (design of modern semiconductor devices) SALUTE studies memory and quantum effects during the femtosecond relaxation process due to electron-phonon interaction in one-band semiconductors or quantum wires there are two main reasons for running this application on the Grid (i) quantum problems are very computationally intensive (ii) the inherently parallel nature of Monte Carlo applications makes efficient use of Grid resources I n this paper we study the quasirandom approach in SALUTE, using the scrambled Halton, Sobol and Niederreiter sequences A large number of tests have been performed on the SEEGRID grid infrastructure using specially developed grid implementation scheme Novel results for energy and density distribution, obtained in the inhomogeneous case with applied electric field are presented

关键词： Grid computing Monte Carlo methods Quasi-Monte Carlo Scrambled Halton Sobol and Niederrerter sequences Ultra-fast carrier transport

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HiAL-Ckpt: A hierarchical application-level checkpointing for CPU-GPU hybrid systems

HiAL-Ckpt: A hierarchical application-level checkpointing fo...

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international conference on Computer Science and Education

作者： Xu, Xinhai Lin, Yufei Tang, Tao Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. the basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool "HiAL-Ckpt". Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. the experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25%, compared with the executing time of SWIM without any FT work. ©2010 IEEE.

关键词： Graphics processing unit

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From NLP (Natural Language processing) to MLP (Machine Language processing)

From NLP (Natural Language Processing) to MLP (Machine Langu...

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5th international conference on Mathematical Methods, Models and architectures for Computer Network Security

作者： Teufl, Peter Payer, Udo Lackner, Guenter Graz Univ Technol Inst Appl Informat Proc & Commun IAIK A-8010 Graz Austria Graz Univ Appl Sci CAMPUS02 Graz Austria Studio 78 Graz Austria

ISBN: (纸本)9783642147050

Natural Language processing (NLP) in combination with Machine Learning techniques plays an important role in the field of automatic text analysis Motivated by the successful use of NLP in solving text classification problems in the area of e-Participation and inspired by our prior work in the field of polymorphic shellcode detection we gave classical NLP-processes a trial in the special case of malicious code analysis Any malicious program is based on some kind of machine language, ranging from manually crafted assembler code that exploits a buffer overflow to high level languages such as Javascript used in web-based attacks We argue that well known NLP analysis processes can be modified and applied to the malware analysis domain Similar to the NLP process we call this process Machine Language processing (MLP) In this paper, we use our e-Participation analysis architecture, extract the various NLP techniques and adopt them for the malware analysis process As proof-of-concept we apply the adopted framework to malicious code examples from Metasploit

关键词： Natural Language processing Malware Analysis Semantic Networks Machine Language processing Machine Learning Knowledge Mining

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