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HiAL-Ckpt: A Hierarchical Application-Level Checkpointing for CPU-GPU Hybrid Systems

HiAL-Ckpt: A Hierarchical Application-Level Checkpointing fo...

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the 5th international conference on Computer Science & Education(第五届国际计算机新技术与教育学术研讨会 ICCSE'10)

作者： Xinhai Xu Yufei Lin Tao Tang Yisong Lin National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. the basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool ”HiAL-Ckpt”. Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. the experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25％, compared with the executing time of SWIM without any FT work.

关键词： GPU:heterogeneous systems:fault-tolerance checkpointing

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Cellular multi-core fusion-tracking system for multi-modal space-time signature analysis

Cellular multi-core fusion-tracking system for multi-modal s...

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IEEE international Workshop on Cellular Nanoscale Networks and their Applications, (CNNA)

作者： Csaba Rekeczky Tibor Kozek Eutecus Inc. Berkeley CA USA Imagize LLC Berkeley CA USA

Summary form only given. A novel real-time signal processing device will be demonstrated designed and implemented for improved target feature extraction, discrimination, and tracking. the device utilizes a unique combination of advanced signal processing techniques for multi-spectral fusion and image analysis. It incorporates state-of-the-art algorithms and the associated electronics to combine the functions of a multi-spectral fusion (MSF) engine and a multi-target tracking and discrimination (MTTD) engine. the resulting compact MSF-MTTD system, currently is capable of processing image flows from two external sensors (e.g. infrared and visible) by utilizing the processing power of massively parallel cellular nonlinear processor architectures at different levels of processing. the compact (<2in ¿ 3) light-weight (<25 g), low-power (<5 W for the entire system) prototype of the multi-core MSF-MTTD engine and system has been implemented using low-power FPGAs and will be used and demonstrated in complex event detection scenarios.

关键词： Signal processing algorithms Engines Target tracking Infrared image sensors Signal design Feature extraction Image analysis Sensor systems Prototypes Field programmable gate arrays

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Design implementation on FPGA of H.264/AVC intra decision frame

Design implementation on FPGA of H.264/AVC intra decision fr...

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international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： H. Loukil A. Ben Atitallah P. Kadionik N. Masmoudi University of Sfax National School of Engineering Sfax TUNISIA University of Sfax High Institute of Electronics and Communication Sfax TUNISIA IMS laboratory-ENSEIRB - University Bordeaux Talence Cedex France

ISBN: (纸本)9781424463381;9781424463404

In this paper, we propose a hardware implementation of H.264 intra frame encoder to achieve the real-time operation for video conference applications. the H.264 intra frame encoder is composed by intra 4×4 prediction, intra 16×16 prediction, integer transform, quantization (AC & DC), inverse integer transform, inverse quantization (AC &DC), hadamard, and inverse hadamard transform. this method can process one macroblock in 573 cycles for all cases of macroblock type. the proposed hardware is implemented in VHDL. the VHDL RTL code works at 100 MHz in an Altera Stratix II FPGA. the execution time is decreased by 30%. the system also includes software running on an NIOS-II processor for implementing the pre-processing and the post-processing function. the H.264 intra frame encoder hardware and software are demonstrated to work together on ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA.

关键词： Field programmable gate arrays Automatic voltage control Energy efficiency Frequency Hardware Discrete wavelet transforms Clocks parallel processing throughput Runtime

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MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time

MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time

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international conference on Embedded and Multimedia Computing (EM-Com)

作者： Roman Bourgade Christine Rochange Marianne De Michiel Pascal Sainrat Institut de Recherche en Informatique de Toulouse University of Toulouse CNRS France

Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while they make it possible to improve the computing power. In order to run real-time software on a multicore architecture, computing the Worst-Case Execution Time of every thread should be achievable. this notably involves bounding memory latencies by employing a predictable bus arbiter. However, state-of-the-art techniques prove to be irrelevant to schedule unbalanced workloads in which some threads require more bus bandwidth than the other ones. this paper proposes a new bus arbitration scheme that ensures that the shared bus latencies can be upper bounded. Compared to other schemes that make the bus latencies predictable, like the Round-Robin protocol, our approach defines several levels of bandwidth to meet requirements that may vary from one thread to another. Experimental results (WCET estimates) show that the worst-case bus latency is noticeably shortened, compared to Round-Robin, for the cores with highest priority that get the largest bandwidth. the relevance of the scheme is shown through an example workload composed of various benchmarks.

关键词： Protocols Instruction sets Delay Processor scheduling Multicore processing Real time systems Benchmark testing

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A mixed style architecture for low power multipliers based on a bypass technique

A mixed style architecture for low power multipliers based o...

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international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： George Economakos Dimitris Bekiaris Kiamal Pekmestzi School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

ISBN: (纸本)9781424463381;9781424463404

In this paper a new technique for the design of combinational circuits for low power is introduced. the basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). the internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures.

关键词： Clocks Delay Energy consumption Switching circuits Integrated circuit interconnections Power dissipation Very large scale integration Digital signal processing Isolation technology Computer architecture

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Cellular multi-core fusion-tracking system

Cellular multi-core fusion-tracking system

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IEEE international Workshop on Cellular Nanoscale Networks and their Applications, (CNNA)

作者： Csaba Rekeczky Tibor Kozek Eutecus Inc. Berkeley CA USA Imagize LLC Berkeley CA USA

ISBN: (纸本)9781424466795;9781424466788

A novel real-time signal processing device has been designed and implemented for improved target feature extraction, discrimination, and tracking. the device utilizes a unique combination of advanced signal processing techniques for multi-spectral fusion and image analysis. It incorporates state-of-the-art algorithm and the associated electronics to combine the functions of a multi-spectral fusion (MSF) engine and a multi-target tracking and discrimination (MTTD) engine. the resulting compact MSF-MTTD system, currently is capable of processing image flows from two external sensors (e.g. infrared and visible) by utilizing the processing power of massively parallel cellular nonlinear processor architectures at different levels of processing. Within this framework topographic data fusion (Stage 1) is followed by parallel feature extraction (Stage 2) and the analysis, tracking and discrimination (Stage 3) of multiple targets at ultra-high frame rates (>1000 fps). the compact (<2in ¿ 3) light-weight (<25 g), low-power (<5 W for the entire system) prototype of the multi-core MSF-MTTD engine and system has been implemented on high-end FPGAs and will be described in this paper.

关键词： Signal processing algorithms Target tracking Engines Feature extraction Infrared image sensors Signal design Image analysis Sensor systems Prototypes Field programmable gate arrays

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A real-time FPGA-based implementation of target detection technique in non homogenous environment

A real-time FPGA-based implementation of target detection te...

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international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Ridha Djemal Electrical Engineering Department College of Engineering King Saud University Saudi Arabia

ISBN: (纸本)9781424463381;9781424463404

this paper presents a high speed real-time target detection system for non homogenous environment based on FPGA Technology. the system implements a Backward Automatic Censored Ordered Statistics Detector (B-ACOSD) to maintain a Constant False Alarm Rate (CFAR) for Radar system with a time constraints in term of signal computing and target identification. the design flow and the hardware implementation of each module are introduced in detail. the proposed system can operate up to 115 MHz by using full pipeline organization and parallel computing which increase the speed up of the target detection system to satisfy the real-time constraints. the proposed architecture is designed, implemented, and tested using Stratix II EP2S60F672C3N FPGA Board. the system has the advantages of being simple, fast, and flexible with low development cost for a reference window of length 16 cells.

关键词： Object detection Real time systems Field programmable gate arrays Statistics Radar detection Detectors Time factors Signal processing Hardware Pipelines

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Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA

Sparse Matrix-Vector Multiplication Based on Network-on-Chip...

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international conference on Computer and Information Technology (CIT)

作者： Chi-Chia Sun Jürgen Götze Hong-Yuan Jheng Shanq-Jang Ruan Information Processing Lab Dortmund University of Technology Dortmund Germany Low-Power System Lab National Taiwan University of Science and Technology Taipei Taiwan

A new method for performing Sparse Matrix-Vector Multiplication (SMVM) by using Network-on-Chip (NoC) architecture is described. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections or shared-buses. therefore, regular local data transfer is the major concern of many parallel implementations. However, when dealing with the parallel implementation of SMVM, which is the main step of all iterative algorithms for solving system of linear equations, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using a NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have implemented the proposed SMVM calculator based on NoC architecture with the size of 4 × 4 and 5 × 5 in IEEE 754 single float point precision using FPGA.

关键词： Sparse matrices Field programmable gate arrays Computer architecture Switches System-on-a-chip Routing Equations

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A Scheduling Method for Avoiding Kernel Lock thrashing on Multi-cores

A Scheduling Method for Avoiding Kernel Lock Thrashing on Mu...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Yan Cui Weida Zhang Yu Chen Yuanchun Shi Department of Computer Science and Technology Tsinghua University China

Multi-core architectures have been adopted in various computing environments. Predictions based on Moore's Law state that thousands of cores can be integrated on a single chip within 10 years. To achieve better performance and scalability on multi-cores, applications should be multi-threaded, and therefore threads assigned on different cores can execute concurrently. However, lock contention in kernels can affect the scalability so significantly that the speedup decreases with the increasing number of cores (thrashing). Existing efforts to address this problem mainly focus on deferring lock thrashing, and therefore these techniques cannot prevent thrashing fundamentally. In this paper, we propose to use lock-aware scheduling to avoid thrashing. Our method detects thrashing on a per-thread basis and migrates contended threads to a smaller set of cores. the optimal number of cores is determined by maximizing the proposed normalized throughput model of migrated threads. the proposed method is implemented in Linux 2.6.29.4 and evaluated on a 32-core system. Experimental results on a series of lock-intensive micro- and macro-benchmarks show the effectiveness: for 3 of 5 workloads exhibiting thrashing behaviour, lock-aware scheduling can detect the speedup decrease accurately and sustain the maximal speedup, for the remaining 2 workloads, the performance can be improved greatly although the maximal speedup is not sustained, for 1 workload which does not suffer thrashing, the method introduces negligible runtime overhead.

关键词： Multicore processing Kernel Instruction sets Linux Benchmark testing throughput Complexity theory

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Design of Generic Floating Point Multiplier and Adder/Subtractor Units

Design of Generic Floating Point Multiplier and Adder/Subtra...

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international conference on Computer Modeling and Simulation, UKSIM

作者： Lamiaa Sayed Abdel Hamid Khaled Shehata Hassan El-Ghitani Mohamed ElSaid ECE Department Misr International University Cairo Egypt ECE Department Arab Academy for Science Technology and Maritime Transport Cairo Egypt ECE Department Ain Shams University Cairo Egypt

A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and used in the multiplier implementation. the new algorithm depends on dividing the multiplication operation into several smaller multiplications performed in parallel. the output from these multiplications is then manipulated in a manner to give the final result of the original multiplication operation. the adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm. In order to achieve high maximum, speed, both units were deeply pipelined. the design is written using VHDL code and mapped to Virtex2, Virtex4 and Virtex5 FPGAs. Both units can operate at more than 400 MHz on Virtex4.

关键词： Signal processing algorithms Field programmable gate arrays Frequency Neck Floating-point arithmetic Hardware Computational modeling Computer simulation Detectors Computer architecture

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