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A paralleled Large-Scale Astronomical Cross-Matching Function

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9th international conference on algorithms and architectures for parallel processing

作者： Zhao, Qing Sun, Jizhou Yu, Ce Cui, Chenzhou Lv, Liqiang Xiao, Jian Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China Chinese Acad Sci Natl Astron Observ Beijing 100012 Peoples R China

ISBN: (纸本)9783642030949

Multi-wavelength data cross-match among multiple catalogs is a basic and unavoidable step to make distributed digital archives accessible and inter-operable. As current catalogs often contain millions or billions objects, it is a typical data-intensive computation problem. In this paper, a high-efficient parallel approach of astronomical cross-match is introduced. We issue our partitioning and parallelization approach, after that we address some problems introduced by task partition and give the solutions correspondingly, including a sky splitting function HEALPix we selected which play a key role on both the task partitioning and the database indexing, and a quick bit-operation algorithm we advanced to resolve the block-edge problem. Our experiments prove that the function has a marked performance superiority comparing with the previous functions and is fully applicable to large-scale cross-match.

关键词： Cross-Match parallel HEALPix Large-Scale Bit-Operation

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High Performance Global Illumination on Multi-core architectures

High Performance Global Illumination on Multi-core Architect...

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17th Euromicro international conference on parallel, Distributed and Network-Based processing

作者： Padron, Emilio J. Amor, Margarita Doallo, Ramon Boo, Montserrat Univ A Coruna Dept Elect & Syst E-15071 La Coruna Spain Univ Santiago de Compostela Dept Elect & Comp Engn E-15782 Santiago De Compostela Spain

ISBN: (纸本)9780769535449

Physically-based illumination is an essential factor for realistic rendering. In this context, hierarchical radiosity is one of the most accurate global illumination methods. One of the key features of the radiosity approach is that it obtains view-independent global illumination results. Unfortunately, global illumination has high computational and memory requirements, and hierarchical radiosity, though more efficient than other radiosity solutions, is not an exception. the progressive popularization of multiprocessor and multi-core processor systems makes the design and implementation of efficient parallel algorithms an appealing alternative in this field. In this paper we present a novel parallel radiosity method addressing the hierarchical radiosity computation on current homogeneous multi-core environments. One of the main contributions of our work is the use of different tasks to exploit the independent interactions among the geometric elements in the scene. Our parallel solution leads to a versatile radiosity implementation that takes advantage of the multiple computational resources in the system, such as multi-core processors and SMT (Simultaneous Multithreading) capabilities. Good results in terms of performance have been achieved.

关键词： Multitasking

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Software Engineering in Practice: Design and architectures of FLOSS Systems 5th

Software Engineering in Practice: Design and Architectures o...

引用

5th international conference on Open Source Systems

作者： Capiluppi, Andrea Knowles, thomas Lincoln Univ Ctr Res Open Source Software Lincoln LN5 7TS England

ISBN: (纸本)9783642020315

Free/Libre/Open Source Software (FLOSS) practitioners and developers are typically also users of their own systems: as a result, traditional software engineering (SE) processes (e.g., the requirements and design phases), take less time to articulate and negotiate among FLOSS developers. Design and requirements are kept more as informal knowledge, rather than formally described and assessed. this paper attempts to recover the SE concepts of software design and architectures from three FLOSS case studies, sharing the same application domain (i.e., Instant Messaging). Its first objective is to determine whether a common architecture emerges from the three systems, which can be used as shared knowledge for future applications. the second objective is to determine whether these architectures evolve or decay during the evolution of these systems. the results of this study are encouraging: albeit no explicit effort was done by FLOSS developers to define a high-level view of the architecture, a common shared architecture could be distilled for the Instant Messaging application domain. It was also found that, for two of the three systems, the architecture becomes better organised, and the components better specified, as long as the system evolves in time.

关键词： Application programs

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the scheduling for press shop based on constraints parallel machine model

The scheduling for press shop based on constraints parallel ...

引用

5th international conference on Natural Computation, ICNC 2009

作者： Yu, Daoyuan Li, Zhengfeng Yang, Shunian School of Mechanical Science and Technology Huazhong University of Science and Technology 430074 Wuhan China

ISBN: (纸本)9780769537368

We presents a new scheduling solution for press shop and a new scheduling model based on constraints parallel machine for press shop. In this paper, the scheduling for press shop is divided into scheduling of one single press line and partitions among several lines. First, the job will be processed from the both terminals of the bidirectional press line and in the order of machines, in which procession the parallel processed jobs are under the constraints of operation number and machine capacity, then the constraints relative between operation and processing time are formulated. Further, the hybrid genetic algorithm with heuristic rules has been developed to solve the problem. Finally, the example of the minimum makespan and balance among press lines is used as the optimized object to validate this model and the scheduling results is obtained which possessed practical application value. © 2009 IEEE.

关键词： Job shop scheduling

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Increasing the Speed of parallel Decoding of Turbo Codes

Increasing the Speed of Parallel Decoding of Turbo Codes

引用

5th international conference on phD Research in MicroElectronics and Electronics

作者： Taskaldiran, Mustafa Morling, Richard C. S. Kale, Izzet Univ Westminster Dept Elect Commun & Software Engn Appl DSP & VLSI Res Grp London W1W 6UW England

ISBN: (纸本)9781424437320

Turbo codes experience a significant decoding delay because of the iterative nature of the decoding algorithms, the high number of metric computations and the complexity added by the (de)interleaver. the extrinsic information is exchanged sequentially between two Soft-Input Soft-Output (SISO) decoders. Instead of this sequential process, a received frame can be divided into smaller windows to be processed in parallel. In this paper, a novel parallel processing methodology is proposed based on the previous parallel decoding techniques. A novel Contention-Free (CF) interleaver is proposed as part of the decoding architecture which allows using extrinsic Log-Likelihood Ratios (LLRs) immediately as a-priori LLRs to start the second half of the iterative turbo decoding. the simulation case studies performed in this paper show that our parallel decoding method can provide %80 time saving compared to the standard decoding and %30 time saving compared to the previous parallel decoding methods at the expense of 0.3dB Bit Error Rate (BER) performance degradation.

关键词： Turbo codes

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VLSI design and analysis of multipliers for low power

VLSI design and analysis of multipliers for low power

引用

IIH-MSP 2009 - 2009 5th international conference on Intelligent Information Hiding and Multimedia Signal processing

作者： Rao, P.V. Raj P, Cyril Prasanna Ravi, S. RNSIT DR.MGR University Chennai India VSDC MSRSAS Bangalore India DR.MGR University India

ISBN: (纸本)9780769537627

Low power multipliers with high clock frequencies play an important role in today's digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. the Layouts of the sub-blocks are drawn using Cadence Virtuoso to form the multipliers macros. DRC and LVS checks are performed using HerculesI and fed to RC-XT for parasitic extraction and to carry out post layout simulation and the power analysis using Astro rail. Delay and Power dissipation of Wallace Tree multiplier is least whereas Array multiplier is a best for reduced area applications but not speed. In this work, the area of 5x5 Array multiplier is 67.73x7μm2 is the least compared to others. Each multiplier has to be selected depending on performance measures and nature of applications. © 2009 IEEE.

关键词： Digital signal processing

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Hardware implement of the forward value conversion algorithm for delta-sigma system based direct stream digital

Hardware implement of the forward value conversion algorithm...

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5th international conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009

作者： Guoxiang, Tong Ming, Chen School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology USST Shanghai China Department of Discrete Devices Shanghai Beiling Corp. Ltd. BL Shanghai China

ISBN: (纸本)9781424436934

Because the parallel data processing and the fast carry-free algorithm can be achieved by using Residue Number System (RNS) in VLSI (very large scale integration) design, RNS (Residue Number System) shows the high performance, such as low power consumption, small area, and short delay, etc. this paper presents the bit stream to RNS converting procedure based on (2 n-1)2n (2n+1) Moduli set. the converting circuit is designed by using Verilog language. the converter in this paper converts directly the bit stream to RNS form, having better application features for Delta-Sigma system based on DSD (direct stream digital). As result, the whole circuit logic is simplified and the circuit characteristic is improved. ©2009 IEEE.

关键词： Digital signal processing

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parallel implementation of good feature extraction for tracking on the cell processor with OpenCV interface

Parallel implementation of good feature extraction for track...

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IIH-MSP 2009 - 2009 5th international conference on Intelligent Information Hiding and Multimedia Signal processing

作者： Sugano, Hiroki Miyamoto, Ryusuke Dept. of Communications and Computer Engineering Kyoto University Yoshida-hon-machi Sakyo Kyoto Japan Dept. of Information Systems Nara Institute of Science and Technology 8916-5 Takayama-cho Ikoma Nara Japan

ISBN: (纸本)9780769537627

One of the most widely used schemes to extract feature points suitable for tracking in computer vision is "Good Features to Track". In this paper, we propose parallel implementation of the good feature extraction scheme optimized for the Cell processor, which is one of the latest high performance embedded processors. By utilizing the computational power of Cell suitable for image processing, we achieve high-speed computation of the operation. Experimental results show that our implementation with 6 SPEs can compute the feature point extraction in 1.4 ms when the input image size is 640 x 480 pixels. this is about 5 times faster than the computation on Intel(R) Core(TM)2 Duo CPU E6850 @ 3.00GHz with Intel Integrated Performance Primitives. this work is part of the CVCell project which is a software library compatible with OpenCV library optimized for the Cell processor. © 2009 IEEE.

关键词： Feature extraction

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Computational experience with nano-material science Quantum Monte Carlo modeling on BlueGene/L

Computational experience with nano-material science Quantum ...

引用

2009 5th international conference on MEMS NANO, and Smart Systems, ICMENS 2009

作者： Sayed, Ahmed El-Shishiny, Hisham IBM Center for Advanced Studies Cairo Egypt

ISBN: (纸本)9780769539386

Modeling and simulation are necessary for nano-material science, as experiments and appliances are costly. In this work we introduce a typical tool flow used for computational nano-material science and report our computational experience with it. QWalk [3] is a Quantum Monte Carlo simulation tool;one of the main methods in identifying nano-material properties, such as the total energy and the band structure of the material. We explain the tool flow for nano-materials and use QWalk to estimate the total energy of selected molecules. We study the tool's use for modeling of molecules at the nano level using three selected molecules and give our experience with QWalk's scalability and the underlying factors affecting it. We discuss the tool's performance, make our recommendations and try to explain some observations. © 2009 IEEE.

关键词： parallel architectures

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Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors

Performance Comparison of Single-Precision SPICE Model-Evalu...

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19th international conference on Field Programmable Logic and Applications

作者： Kapre, Nachiket DeHon, Andre CALTECH Comp Sci Pasadena CA 91125 USA Univ Penn Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (纸本)9781424438914

Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE Model-Evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, Pthreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3 182 x for a Xilinx Virtex5 LX 330T, 1.3-33x for an IBM Cell, and 3-131 x for an NVIDIA 9600 GT CPU over a 3 GHz Intel Xeon 5160 implementation for a variety of single-precision device models.

关键词： Graphics processing unit

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