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DISTRIBUTED CLOSED-LOOP QUASI-ORthOGONAL SPACE TIME BLOCK CODING WIth FOUR RELAY NODES: OVERCOMING IMPERFECT SYNCHRONIZATION

DISTRIBUTED CLOSED-LOOP QUASI-ORTHOGONAL SPACE TIME BLOCK CO...

引用

5th Annual IEEE international conference on Wireless and Mobile Computing, Networking and Communications

作者： Elazreg, A. M. Abdurahman, F. M. Chambers, J. A. Univ Loughborough Dept Elect & Elect Engn Adv Signal Proc Grp Loughborough LE11 3TU Leics England

ISBN: (纸本)9781424453337

In this paper, closed-loop quasi-orthogonal space time block coding (QO-STBC) is exploited within a four relay node transmission scheme to achieve full-rate and increase the available diversity gain provided by earlier two relay approaches. the problem of imperfect synchronization between relay nodes is overcome by applying a parallel interference cancellation (PIC) detection scheme at the destination node. Bit error rate simulations confirm the advantages of the proposed methodology for a range of levels of imperfect synchronization and that only a small number of iterations is necessary within the PIC detection.

关键词： Closed-loop quasi-orthogonal space time block coding (CL QO-STBC) closed-loop phase rotated feedback linear processing and parallel interference cancellation detection (PIC)

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FPGA Accelerating three QR Decomposition algorithms in the Unified Pipelined Framework

FPGA Accelerating Three QR Decomposition Algorithms in the U...

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19th international conference on Field Programmable Logic and Applications

作者： Yong Dou Zhou, Jie Chen, Xiaoyang Lei, Yuanwu Xu, Jinbo Natl Univ Def Technol Natl Lab Parallel & Distributed Proc Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781424438914

Many FPGA implementations for QR decomposition have been studied on small-scale matrix and all of them are presented individually. However to the best of our knowledge, there is no FPGA-based accelerator for large-scale QR decomposition. In this paper, we propose a unified FPGA accelerator structure for large-scale QR decomposition. To exploit the computational potential of FPGA, we introduce a fine-grained parallel algorithm for QR decomposition. A scalable linear array processing elements (PEs), which is the core component of the FPGA accelerator;is proposed to implement this algorithm. A total of 15 PEs can integrated into an Altera StratixII EP2S130F1020C5 on our self-designed board. Experimental results show that a factor of 4 speedup and the maximum power-performance of 60.9 can be achieved compare to Pentium Dual CPU with double SSE thread.

关键词： Field programmable gate arrays (FPGA)

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RECURSIVE DUAL-NET: A NEW VERSATILE NETWORK FOR SUPERCOMPUTERS OF thE NEXT GENERATION

RECURSIVE DUAL-NET: A NEW VERSATILE NETWORK FOR SUPERCOMPUTE...

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9th international conference on algorithms and architectures for parallel processing

作者： Li, Yamin Peng, Shietung Chu, Wanming Hosei Univ Dept Comp Sci Tokyo 1848584 Japan Univ Aizu Dept Comp Hardware Aizu Wakamatsu Fukushima 9658580 Japan

In this paper, we propose a new versatile network, called a recursive dual-net (RDN), as a potential candidate for the interconnection network of supercomputers of the next generation. the RDN is based on recursive dual-construction of a base network. A k-level recursive dual construction for k > 0 creates a network containing (2m)2(k)/2 nodes with node-degree d + k, where in and d are the number of nodes and the node-degree of the base network, respectively. the RDN is node and edge symmetric if the base network is node and edge symmetric. the RDN can contain a huge number of nodes, each with small node-degree and short diameter. For example, we can construct a symmetric RDN connecting more than 3-million nodes with only 6 links per node and a diameter of 22. We investigate the topological properties of the RDN and compare them to those of other networks including 3D torus, WK-recursive network, hypercube, cube-connected-cycle, and dual-cube. We also establish the efficient routing and broadcasting algorithms for the RDN.

关键词： parallel processing interconnection network

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AN EFFICIENT SORTING ALGORIthM WIth CUDA

AN EFFICIENT SORTING ALGORITHM WITH CUDA

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9th international conference on algorithms and architectures for parallel processing

作者： Chen, Shifu Qin, Jing Xie, Yongming Zhao, Junping Heng, Pheng-Ann Chinese Univ Hong Kong Chinese Acad Sci Shenzhen Inst Adv Integrat Technol Hong Kong Hong Kong Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Chinese PLA Gen Hosp & Postgrad Med Sch Inst Med Informat Beijing Peoples R China

An efficient GPU-based sorting algorithm is proposed in this paper together with a merging method on graphics devices. the proposed sorting algorithm is optimized for modern GPU architecture with the capability of sorting elements represented by integers, floats and structures, while the new merging method gives a way to merge two ordered lists efficiently on GPU without using the slow atomic functions and uncoalesced memory read. Adaptive strategies are used for sorting disorderly or nearly-sorted lists, large or small lists. the current implementation is on NVIDIA CUDA with multi-GPUs support, and is being migrated to the new born Open Computing Language (OpenCL). Extensive experiments demonstrate that our algorithm has better performance than previous GPU-based sorting algorithms and can support real-time applications.

关键词： parallel sorting parallel merging CUDA

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DATA-parallel TECHNIQUES FOR AGENT-BASED TISSUE MODELING ON GRAPHICS processing UNITS

DATA-PARALLEL TECHNIQUES FOR AGENT-BASED TISSUE MODELING ON ...

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ASME international Design Engineering Technical conferences/Computers and Information in Engineering conference

作者： Richards, Ryan S. Lysenko, Mikola D'Souza, Roshan M. An, Gary Michigan Technol Univ Dept Comp Sci Houghton MI 49931 USA

ISBN: (纸本)9780791843277

Agent-Based Modeling has been recently recognized as a method for in-silico multi-scale modeling of biological cell systems. Agent-Based Models (ABMs) allow results from experimental studies of individual cell behaviors to be scaled into the macro-behavior of interacting cells in complex cell systems or tissues. Current generation ABM simulation toolkits are designed to work on serial von-Neumann architectures, which have poor scalability. the best systems can barely handle tens of thousands of agents in real-time. Considering that there are models for which mega-scale populations have significantly different emergent behaviors than smaller population sizes, it is important to have the ability to model such large scale models in real-time. In this paper we present a new framework for simulating ABMs on programmable graphics processing units (GPUs). Novel algorithms and data-structures have been developed for agent-state representation, agent motion, and replication. As a test case, we have implemented an abstracted version of the Systematic Inflammatory Response System (SIRS) ABM. Compared to the original implementation on the NetLogo system, our implementation can handle an agent population that is over three orders of magnitude larger with close to 40 updates/sec. We believe that our system is the only one of its kind that is capable of efficiently handling realistic problem sizes in biological simulations.

关键词： Graphics processing unit

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A GPU-based simulation of tsunami propagation and inundation

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9th international conference on algorithms and architectures for parallel processing, ICA3PP 2009

作者： Liang, Wen-Yew Hsieh, Tung-Ju Satria, Muhammad T. Chang, Yang-Lang Fang, Jyh-Perng Chen, Chih-Chia Han, Chin-Chuan Department of Computer Science and Information Engineering Taiwan Department of Electrical Engineering National Taipei University of Technology Taiwan Department of Computer Science and Information Engineering National United University Taiwan

ISBN: (纸本)3642030947

Tsunami simulation consists of fluid dynamics, numerical computations, and visualization techniques. Nonlinear shallow water equations are often used to model the tsunami propagation. By adding the friction slope to the conservation of momentum, it also can model the tsunami inundation. To solve these equations, we use the second order finite difference MacCormack method. Since it is a finite difference method, it brings the possibility to be parallelized. We use the parallelism provided by GPU to speed up the computations. By loading data as textures in GPU memory, the computation processes can be written as shader programs and the operations will be done by GPU in parallel. the results show that with the help of GPU, the simulation can get a significant improvement in the execution time for each of the computation steps. © 2009 Springer Berlin Heidelberg.

关键词： Graphics processing unit

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Atune-IL: An Instrumentation Language for Auto-tuning parallel Applications

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15th international Euro-Par conference on parallel Computing

作者： Schaefer, Christoph A. Pankratius, Victor Tichy, Walter F. Univ Karlsruhe TH D-76131 Karlsruhe Germany

ISBN: (纸本)9783642038686

Auto-tuners automate the performance toning of parallel applications. three major drawbacks of current approaches are I.) they mainly focus Oil numerical software;2) they typically do riot attempt;to reduce the large search space: before search algorithms are applied;3) the means to provide an auto-turner with additional information to improve tuning are limited. Our paper tackles these problems in a novel way by focusing on the interaction between art auto-toner and a parallel application. In particular;we introduce Atune-IL, an instrumentation language that uses new tykes of code annotations to mark tuning parameters, blocks, permutation regions, and measuring points. Atune-IL allows a more accurate extraction of meta-information to help an auto-tuner prune the search space before employing search algorithms. In addition, Atune-IL's Concepts target parallel applications in general, not just numerical programs. Atune-IL has been successfully evaluated in several case studies with parallel applications differing in size;programming language;and application domain;one case study employed a. large commercial application with nested parallelism. On average;Atune-IL reduced search spaces by 78%. In two corner cases, 99% of the search space could be pruned.

关键词： Application programs

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Developing the KMKE Knowledge Management System Based on Design Patterns and parallel processing

Developing the KMKE Knowledge Management System Based on Des...

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5th international conference on Intelligent Computing

作者： Lai, Lien-Fu Wu, Chao-Chin Huang, Liang-Tsung Chang, Ya-Chin Department of Computer Science and Information Engineering National Changhua University of Education Taiwan Department of Information Communication MingDao University Taiwan

ISBN: (纸本)9783642040696

KMKE provides a knowledge engineering approach to integrating knowledge management activities (such as knowledge modeling, knowledge verification, knowledge storage and knowledge querying) into a systematic framework. In this paper, we develop the KMKE knowledge management system based on design patterns and parallel processing. First, several design patterns are applied to develop the KMKE system for enhancing its flexibility and extensibility. Making the KMKE system flexible and extensible is useful to deal with continuous changes originated in knowledge. Second, JAVA programs and CLIPS programs are bound to offer the capability of knowledge inference for the KMKE system. Knowledge verification and knowledge querying can then be performed through the execution of CLIPS rules. Finally, we propose the parallel CLIPS to shorten the execution time of the KMKE system. Since a large amount of knowledge may increase the execution time substantially, parallelizing the execution of CLIPS rules in cluster system could effectively reduce the search space of the CLIPS inference engine.

关键词： Knowledge Engineering Knowledge Management Expert Systems Design Patterns parallel processing

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Fabrication of terahertz wave resonators of twinned photonic crystals with alumina diamond lattices by using micro-stereolithography

Fabrication of terahertz wave resonators of twinned photonic...

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5th international conference on Ceramic Interconnect and Ceramic Microsystems Technologies, CICMT 2009

作者： Niki, Toshiki Kirihara, Soshu Smart Processing Research Center Joining and Welding Research Institute Osaka University 11-1 Mihogaoka Ibaraki Osaka 567-0047 Japan

ISBN: (纸本)9781615673742

Micrometer order diamond photonic crystals composed of alumina were fabricated by using a micro-stereolithography of computer aided design and manufacturing systems and powder sintering processes. Twinned structures with mirror symmetric diamond lattices were designed to introduce defect interfaces parallel to (100) and (111) planes. Electromagnetic wave properties were measured by using a terahertz time domain spectroscopy. A perfect photonic band gap was observed in a terahertz wave frequency range, and showed good agreement with theoretical calculations by using a plane wave expansion method. Transmission peaks of localized modes were formed in the band gaps through the twinned diamond structures. In distribution profiles of electric field intensities simulated by using a transmission line modeling method, incident waves were resonated and localized strongly through multiple reflections between the twinned diffraction lattices. the stronger localized mode of transmission peak with the higher intensity was obtained between through structural modifications of the twinned lattice patterns.

关键词： Terahertz waves

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A Real-Time Occlusion Aware Hardware Structure for Disparity Map Computation

A Real-Time Occlusion Aware Hardware Structure for Disparity...

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15th international conference on Image Analysis and processing (ICIAP 2009)

作者： Georgoulas, Christos Andreadis, Ioannis Democritus Univ Thrace Dept Elect & Comp Engn Elect Lab GR-67100 Xanthi Greece

ISBN: (纸本)9783642041457

Many machine vision applications deal with depth estimation in a scene. Disparity map recovery from a stereo image pair has been extensively studied by the computer vision community. Previous methods are mainly restricted to software based techniques on general-purpose architectures, presenting relatively high execution time due to the computationally complex algorithms involved. In this paper a new hardware module suitable for real-time disparity map computation module is realized. this enables a hardware based occlusion-aware parallel-pipelined design, implemented on a single FPGA device with a typical operating frequency of 511 MHz. It provides accurate disparity map computation at a rate of 768 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640x480 pixel spatial resolution. the proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.

关键词： FPGA-hardware implementation occlusions real-time imaging disparity maps color image processing

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