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Meta-learning enhancements by data partitioning

Meta-learning enhancements by data partitioning

引用

IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Beata Merk Camelia Vidrighin Bratu Rodica Potolea Technical University of Cluj Napoca Romania

In data mining, there is no learning algorithm which attains the highest accuracy on any dataset. Multilevel arbiter and combiner arbiter are presented in this paper, as techniques to integrate classifiers induced from partitioned data, having as optimization criterion the accuracy of a given dataset. Experimental evaluations have shown that an arbiter tree can be found having similar or higher predictive performance when compared to the accuracy of the individual learner, trained on the entire training set. Moreover, for multiclass dataset with unbalanced class distribution, the combiner arbiter strategy yielded a good improvement in the prediction performance level.

关键词： Buildings Classification tree analysis Partitioning algorithms Tree data structures Data mining Training data parallel processing Accuracy Testing Performance evaluation

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Design of low power multimode time-shared filters

Design of low power multimode time-shared filters

引用

international conference on Information, Communications and Signal processing

作者： Navin Michael A.P. Vinod Christophe Moy Jacques Palicot School of Computer Engineering Nanyang Technological University Singapore Singapore School of Computer Engineering Nanyang Technological University Singapore SUPELEC/IETR Rennes France

ISBN: (纸本)9781424446568

this paper proposes a new class of time-shared filtering architectures targeted at low power multimode portable wireless applications. the proposed structures exploit the increased cycle period available in fast filter algorithm based parallel processing structures to operate at a lower supply voltage, thereby reducing the power consumption. Further power reductions are obtained due to the reduced number of multiplications in fast filter algorithms. the paper also presents a novel power consumption model for various time-shared filter architectures in a voltage scaling regime. the proposed model can be used to investigate the impact of varying the throughput, filter architecture, filter lengths, and parallelism on the power consumption.

关键词： Power filters Finite impulse response filter Energy consumption throughput Hardware Dynamic voltage scaling parallel processing Filtering algorithms Costs Capacitance

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Partitioned Computation to Accelerate Scalar Multiplication for Elliptic Curve Cryptosystems

Partitioned Computation to Accelerate Scalar Multiplication ...

引用

international conference on parallel and Distributed Systems (ICPADS)

作者： Keke Wu Dawei Li Huiyun Li Tingding Chen Fengqi Yu CAS Shenzhen Institute of Advanced Technology Beijing China Chinese Academy and Sciences Beijing China Institute of VLSI Design University of Zhejiang Hangzhou China CAS Shenzhen Institute of Advanced Technology Shenzhen China

the scalar multiplication is the dominant operation in Elliptic Curve Cryptosystems (ECC). It consists of a series of point additions and point doublings. A number of algorithms have been proposed to accelerate the scalar multiplication. Most of the algorithms demand high complexity which makes scalar multiplication hard to implement. In this paper, we propose an efficient algorithm for computing scalar multiplication based on partitioning scalar and propositional logic theory to address the trade-offs between speed and complexity. Our algorithm remains low complexity compared to existing accelerated scalar multiplication algorithms, whilst it is suitable for parallel processing systems.

关键词： Acceleration Elliptic curve cryptography Partitioning algorithms Logic Elliptic curves parallel architectures Security Content addressable storage Personal digital assistants Galois fields

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parallel Discrete Event Simulation of Molecular Dynamics through Event-Based Decomposition

Parallel Discrete Event Simulation of Molecular Dynamics Thr...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Martin C. Herbordt Md. Ashfaquzzaman Khan Tony Dean Department of Electrical and Computer Engineering Boston University Boston MA USA

Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized models, enabling simulations to be advanced by event, with a resulting performance increase of several orders of magnitude. Even so, DMD is compute bound. Moreover, unlike MD, causality issues make DMD difficult to scale. Here we present a microarchitecture-inspired parallel algorithm for DMD: speculative execution enables multithreading, while in-order commitment ensures correctness. Our initial not-yet optimized implementation obtains scalability for a multicore processor when running realistic simulation models.

关键词： Discrete event simulation Computational modeling Biological system modeling Computer simulation Computer architecture Microarchitecture parallel algorithms Multithreading Scalability Multicore processing

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A Massively parallel Approach to Affine Transformataion in Medical Image Registration

A Massively Parallel Approach to Affine Transformataion in M...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Huynh Van Luong Jong-Myon Kim University of Ulsan Ulsan KR School of Computer Engineering and Information Technology University of Ulsan Ulsan Korea

Medical image registration plays an important role in investigating disease processes and understanding normal development and ageing. An essential component in most medical registration approaches is affine transformation. the affine transformation is made up of any combination of linear transformations (rotation and scaling) followed by translation. these algorithms are generally computationally expensive. the increasing availability of parallel computers makes parallelizing these tasks an attractive option. this paper proposes a massively parallel approach for affine transformations using a representative data parallel architecture to accelerate such algorithms. the result of our parallel approach is outstanding in terms of both processing performance and energy efficiency. the proposed parallel approach achieves a three order of computational capabilities and a second order of energy efficiency of other implementations using commercial processors such as TI DSP and ARM families.

关键词： Biomedical imaging Image registration Concurrent computing Energy efficiency Diseases Aging Availability parallel architectures Acceleration Digital signal processing

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Real-time predictability on multi-processor and multi-core architectures

Real-time predictability on multi-processor and multi-core a...

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IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Gheorghe Sebestyen Ramona Marfievici Department of Computer Science Technical University of Cluj Napoca Cluj-Napoca Romania

this article presents a number of real-time predictability issues and also some opportunities for improving the worst case execution time (WCET) of concurrent real-time threads on multi-core and multiprocessor systems. the authors analyze the real-time behavior of such systems in a number of scenarios, where thread affinity and co-scheduling techniques are used. the experimental results validate the analytically determined WCET values.

关键词： Processor scheduling Real time systems Yarn Operating systems Java Multiprocessing systems Frequency synchronization Predictive models Multicore processing Virtual machining

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Scalability of efficient parallel K-Means

Scalability of efficient parallel K-Means

引用

IEEE international conference on E-Science Workshops

作者： David Pettinger Giuseppe Di Fatta School of Systems Engineering University of Reading Reading Berkshire UK

Clustering is defined as the grouping of similar items in a set, and is an important process within the field of data mining. As the amount of data for various applications continues to increase, in terms of its size and dimensionality, it is necessary to have efficient clustering methods. A popular clustering algorithm is K-Means, which adopts a greedy approach to produce a set of K-clusters with associated centres of mass, and uses a squared error distortion measure to determine convergence. Methods for improving the efficiency of K-Means have been largely explored in two main directions. the amount of computation can be significantly reduced by adopting a more efficient data structure, notably a multi-dimensional binary search tree (KD-Tree) to store either centroids or data points. A second direction is parallel processing, where data and computation loads are distributed over many processing nodes. However, little work has been done to provide a parallel formulation of the efficient sequential techniques based on KD-Trees. Such approaches are expected to have an irregular distribution of computation load and can suffer from load imbalance. this issue has so far limited the adoption of these efficient K-Means techniques in parallel computational environments. In this work, we provide a parallel formulation for the KD-Tree based K-Means algorithm and address its load balancing issues.

关键词： Scalability Concurrent computing Distributed computing Data mining Clustering methods Clustering algorithms Distortion measurement Convergence Tree data structures Binary search trees

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parallel Carrier Recovery in All-Digital Receiver

Parallel Carrier Recovery in All-Digital Receiver

引用

international conference on Wireless Communications, Networking and Mobile Computing (WiCom)

作者： Yingjian Wang Yu Zhang Zhixing Yang Department of Electronic Engineering Tsinghua National Laboratory of Information Science and Technology (TNLIST) Tsinghua University Beijing China

In this paper, a parallel carrier recovery method for all-digital receiver is proposed. Unlike the existing serial carrier recovery method, which makes the carrier recovery for one symbol at a time, the parallel structure makes the carrier recovery for one frame at a time, characterized by vector-operation of the vector phase error and control word. this trait dramatically lightens the hardware-constraint and improves the processing rate of the receiver with no additional performance loss. Besides, simplified structures of the parallel carrier recovery and their performance losses are also discussed.

关键词： Frequency estimation Timing Matched filters Performance loss Phase control Laboratories Information science Error correction parallel processing Phase detection

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Intelligent cores and intelligent agents: Two approaches to achieve autonomy in Swarm-Array Computing

Intelligent cores and intelligent agents: Two approaches to ...

引用

IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Blesson Varghese Gerard McKee School of Systems Engineering University of Reading UK

How can a bridge be built between autonomic computing approaches and parallel computing systems? How can autonomic computing approaches be extended towards building reliable systems? How can existing technologies be merged to provide a solution for self-managing systems? the work reported in this paper aims to answer these questions by proposing swarm-array computing, a novel technique inspired from swarm robotics and built on the foundations of autonomic and parallel computing paradigms. Two approaches based on intelligent cores and intelligent agents are proposed to achieve autonomy in parallel computing systems. the feasibility of the proposed approaches is validated on a multi-agent simulator.

关键词： Intelligent agent Biology computing parallel processing Concurrent computing Distributed computing Cloud computing Computer vision Field programmable gate arrays Hardware Space technology

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Analog multiplier for a low-power integrated image sensor

Analog multiplier for a low-power integrated image sensor

引用

international conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Grzegorz Blakiewicz Microelectronic Systems Gdansk University of Technology Gdansk Poland

this paper presents a new approach to an integrated low-power and low-cost image sensor design. A matrix multiplier is proposed as a better alternative to known massively parallel architectures. the circuit, although less flexible in number of possible to implement algorithms, characterizes very low power consumption and occupied chip area. the presented circuit is designed using 0.35 mum two polysilicon, three metal CMOS technology. It consumes about 8 mW of supply power and occupies 15 mm 2 including photoreceptor matrix. A similar solution based on a massively parallel architecture needs 250 mW of supply power and occupies 40 mm 2 of chip area.

关键词： Image sensors Kernel parallel architectures Energy consumption Circuits CMOS technology Photoreceptors Image processing CMOS image sensors Power supplies

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