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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"
3304 条 记 录,以下是2191-2200 订阅
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parallel Dense Gauss-Seidel Algorithm on Many-Core Processors
Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...
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IEEE international conference on High Performance Computing and Communications (HPCC)
作者: Hadrien Courtecuisse Jérémie Allard INRIA Lille Nord Europe France
the Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited ... 详细信息
来源: 评论
High Performance Digital Carrier Tracking Loop Design for High Dynamic GPS Receiver
High Performance Digital Carrier Tracking Loop Design for Hi...
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international conference on Wireless Communications, Networking and Mobile Computing (WiCom)
作者: Yan Yang Zhengquan Huang State Key Laboratory of Rail Traffic Control and Safety Beijing Jiaotong University Beijing China Institute of Information Engineering Beijing University of Posts and Telecommunications Beijing China
A high efficiency carrier tracking loop to deals with high dynamic circumstance GPS receiver was presented in this paper. Based on FFT parallel capture method, fast frequency discrimination and its realization scheme ... 详细信息
来源: 评论
A FPGA-based parallel Architecture for Scalable High-Speed Packet Classification
A FPGA-based Parallel Architecture for Scalable High-Speed P...
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IEEE international conference on Application-specific Systems, architectures and Processors
作者: Weirong Jiang Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California
Multi-field packet classification is a critical function that enables network routers to support a variety of applications such as firewall processing, Quality of Service differentiation, traffic billing, and other va... 详细信息
来源: 评论
A data-flow graph generation algorithm for a coarse-grained reconfigurable processor
A data-flow graph generation algorithm for a coarse-grained ...
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international conference on ASIC
作者: Chao Yang Shouyi Yin Leibo Liu Shaojun Wei Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing China Tsinghua University Beijing Beijing CN
In this paper, we present a C-to-DFG generation algorithm for coarse-grained reconfigurable processor in multimedia application field. the algorithm exploits the operation parallelism available in the sequential code;... 详细信息
来源: 评论
parallel Approach to Fuzzy Vector Quantization for Image Compression
Parallel Approach to Fuzzy Vector Quantization for Image Com...
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ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing (SNPD)
作者: Huynh Van Luong Yong-Min Kim Byung-Kook Kim Jong-Myon Kim Cheol-Hong Kim School of Computer Engineering and Information Technology University of Ulsan Ulsan Korea School of Electronics and Computer Engineering Chonnam National University Gwangju Korea
Fuzzy clustering based vector quantization algorithm has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this ... 详细信息
来源: 评论
Chipcflow- A dynamic dataflowmachine using dynamic reconfigurable hardware
Chipcflow- A dynamic dataflowmachine using dynamic reconfigu...
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Southern conference on Programmable Logic
作者: Jorge L. Silva Joelmir J. Lopes Valentin O. Roda Kelton P. Costa Department of Computer Systems University of Sao Paulo Sao Paulo Brazil Department of Electrical Engineering University of Sao Paulo Sao Paulo Brazil
In order to convert High Level Language (HLL) into hardware, a Control Dataflow Graph (CDFG) is a fundamental element to be used. Otherwise, Dataflow Architecture, can be obtained directly from the CDFG. In the 1970s ... 详细信息
来源: 评论
A High-Performance Hardware Architecture for Spectral Hash Algorithm
A High-Performance Hardware Architecture for Spectral Hash A...
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international conference on Application Specific Systems (ASAP), architectures and Processors
作者: Ray C.C. Cheung Çetin K. Koc John D. Villasenor City University of Hong Kong Hong Kong China Electrical Engineering Department UCLA Los Angeles CA USA Computer Science Department University of California슠Santa Barbara Santa Barbara CA USA
the spectral hash algorithm is one of the round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete Fourier transformations over a finite fie... 详细信息
来源: 评论
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA...
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international conference on Reconfigurable Computing and FPGAs (ReConFig)
作者: Jiang Jiang Vincent Mirian Kam Pui Tang Paul Chow Zuocheng Xing School of Computer National University of Defense Technology Changsha Hunan China Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada
In this paper, we introduce a scalable macro-pipelined architecture to perform floating point matrix multiplication, which aims to exploit temporal parallelism and architectural scalability. We demonstrate the functio... 详细信息
来源: 评论
AN EFFICIENT SORTING ALGORIthM WIth CUDA
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JOURNAL OF thE CHINESE INSTITUTE OF ENGINEERS 2009年 第7期32卷 915-921页
作者: Chen, Shifu Qin, Jing Xie, Yongming Zhao, Junping Heng, Pheng-Ann Chinese Univ Hong Kong Chinese Acad Sci Shenzhen Inst Adv Integrat Technol Hong Kong Hong Kong Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Chinese PLA Gen Hosp & Postgrad Med Sch Inst Med Informat Beijing Peoples R China
An efficient GPU-based sorting algorithm is proposed in this paper together with a merging method on graphics devices. the proposed sorting algorithm is optimized for modern GPU architecture with the capability of sor... 详细信息
来源: 评论
RECURSIVE DUAL-NET: A NEW VERSATILE NETWORK FOR SUPERCOMPUTERS OF thE NEXT GENERATION
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JOURNAL OF thE CHINESE INSTITUTE OF ENGINEERS 2009年 第7期32卷 931-938页
作者: Li, Yamin Peng, Shietung Chu, Wanming Hosei Univ Dept Comp Sci Tokyo 1848584 Japan Univ Aizu Dept Comp Hardware Aizu Wakamatsu Fukushima 9658580 Japan
In this paper, we propose a new versatile network, called a recursive dual-net (RDN), as a potential candidate for the interconnection network of supercomputers of the next generation. the RDN is based on recursive du... 详细信息
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