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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3284 条记录，以下是241-250 订阅

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Mining of association rules in very large databases: A structured parallel approach

Mining of association rules in very large databases: A struc...

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5th international Euro-Par conference

作者： Becuzzi, P Coppola, M Vanneschi, M Univ Pisa Dipartimento Informat I-56100 Pisa Italy

ISBN: (纸本)3540664432

Newer and newer parallel architectures being developed raise a strong demand for high-level and programmer-friendly parallel tools. We show some results regarding mining of association rules, a well-known Data Mining algorithm, which we ported from sequential to parallel within the PQE2000/SkIE environment. the main goals achieved are the low effort spent in parallelizing the code, the machine independence of the application produced, source code portability and performance portability. Here we report test results for the same parallel program on three different architectures.

关键词： parallel architectures

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MEDICS: Ultra-Portable processing for Medical Image Reconstruction 10

MEDICS: Ultra-Portable Processing for Medical Image Reconstr...

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19th international conference on parallel architectures and Compilation Techniques

作者： Dasika, Ganesh Sethia, Ankit Robby, Vincentius Mudge, Trevor Mahlke, Scott Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781450301787

Medical imaging provides physicians with the ability to generate 3D images of the human body in order to detect and diagnose a wide variety of ailments. Making medical imaging portable and more accessible provides a unique set of challenges. In order to increase portability, the power consumed in image acquisition - currently the most power-consuming activity in an imaging device - must be dramatically reduced. this can only be done, however, by using complex image reconstruction algorithms to correct artifacts introduced by low-power acquisition, resulting in image processing becoming the dominant power-consuming task. Current solutions use combinations of digital signal processors, general-purpose processors and, more recently, general-purpose graphics processing units for medical image processing. these solutions fall short for various reasons including high power consumption and an inability to execute the next generation of image reconstruction algorithms. this paper presents the MEDICS architecture a domain-specific multicore architecture designed specifically for medical imaging applications, but with sufficient generality to make it programmable. the goal is to achieve 100 GFLOPs of performance while consuming orders of magnitude less power than the existing solutions. MEDICS has a throughput of 128 GFLOPs while consuming as little as 1.6W of power on advanced CT reconstruction applications. this represents up to a 20X increase in computation efficiency over current designs.

关键词： Low power Medical imaging Operation chaining Stacked DRAM Stream processing

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Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores 26

Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Trabes, Guillermo Gil-Costa, Veronica Printista, Marcela Marin, Mauricio Univ Nacl San Luis Dept Informat LIDIC San Luis Argentina Univ Nacl San Luis San Luis Argentina CCT San Luis CONICET San Luis Argentina Univ Santiago Chile CeBiB Santiago Chile

ISBN: (纸本)9781538649756

Computer models have been used as a bridge between parallel algorithms and hardware architectures. the Bulk-Synchronous parallel (BSP) is a well-known computing model originally devised for distributed algorithms running on clusters of single-core processors. the Multi-BSP model, that extends the classic BSP model, was recently proposed for multi-core processors. However, this model - implemented through the MulticoreBSP-for-C library-presents some restrictions such as the explicit synchronizations between the cores, introducing some challenges on which the hardware characteristics should be taken into account to properly model the parallel algorithms. therefore, we explore the suitability of these models for the Dell multi-core architecture. the objectives of this contribution are twofold. First, we model two different multi-core Dell architectures. Second, we show that a simple model with few parameters can be easily adapted to each Dell platform rather than complex models which tends to use tricky hardware parameters.

关键词： parallel computing models bulk-synchronous parallel - BSP Multi-BSP Dell multi-cores

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algorithms and architectures for parallel processing 1

引用

丛书名： Lecture Notes in Computer Science

1000年

作者： Xian-he Sun Wenyu Qu Ivan Stojmenovic Wanlei Zhou Zhiyang Li Hua Guo Geyong Min Tingting Yang Yulei Wu Lei Liu

ISBN: (数字)9783319111940

ISBN: (纸本)9783319111933

this two volume set LNCS 8630 and 8631 constitutes the proceedings of the 14th international conference on algorithms and architectures for parallel processing, ICA3PP 2014, held in Dalian, China, in August 2014. the 70 revised papers presented in the two volumes were selected from 285 submissions. the first volume comprises selected papers of the main conference and papers of the 1st international Workshop on Emerging Topics in Wireless and Mobile Computing, ETWMC 2014, the 5th international Workshop on Intelligent Communication Networks, IntelNet 2014, and the 5th international Workshop on Wireless Networks and Multimedia, WNM 2014. the second volume comprises selected papers of the main conference and papers of the Workshop on Computing, Communication and Control Technologies in Intelligent Transportation System, 3C in ITS 2014, and the Workshop on Security and Privacy in Computer and Network Systems, SPCNS 2014.

关键词： Algorithm Analysis and Problem Complexity Software Engineering Computer Communication Networks Database Management

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Performance analysis of PDE based parallel algorithms on different computer architectures

Performance analysis of PDE based parallel algorithms on dif...

引用

5th international conference on Soft Computing, Computing with Words and Perceptions in System Analysis, Decision and Control, ICSCCW 2009

作者： Kopan, Ilker Çelebi, M. Serdar Informatics Institute Computational Science and Engineering Program ITU Istanbul Turkey

ISBN: (纸本)9781424434282

Performance of an algorithm mainly depends on both computer architecture and software. An Intel Xeon processor based HPC cluster and Intel Itanium2 based symmetric multiprocessing (SMP) architectures are used for performance analysis of PDE based parallel algorithm. Algorithm is parallelized using MPI and performance measurements are done using Tuning and Analysis Utilities (TAU). Computational optimization reveals data independency and helps compiler to generate more efficient program for that specific processor. Removing data dependency inside loop is the key in this work. In iterative algorithms, like Gauss-Seidel method, each processor communicates with the same processors at every iteration. this feature makes persistent connection preferable. MPI has different types of communication methods for different communication characteristics. Persistent connection is one of them. Persistent connection removes connection overhead by leaving connection open for further communications. It can be preferred if data is transferred repeatedly between same nodes. In this work source code changed to help compiler to generate more efficient program for the specific processor. Also MPI persistent connection is used for communication at each iteration in Gauss-Seidel method. In some parallel algorithms, communication must be synchronized. Making communication between processors at the same time becomes a bottleneck if communication medium is shared. this fact has been studies and analyzed. ©2009 IEEE.

关键词： parallel algorithms

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A Post-processing Approach in Moving Objects Detection via Feature Pyramid Networks 9

A Post-Processing Approach in Moving Objects Detection via F...

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9th international conference on parallel architectures, algorithms and Programming (PAAP)

作者： Lin, Li Wang, Bin Gu, Yinjuan Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai Peoples R China Shanghai Univ Sch Commun & Informat Engn Shanghai Peoples R China

ISBN: (纸本)9781538694039

Recent work has shown that Convolutional Neural Networks (CNNs) have great ability to deal with classification problems in pattern recognition field. Moving objects detection, regarding as a classification process, labels every pixel as a foreground pixel or a background pixel. In this paper, we proposed an effective post-processing approach, Residual Background Networks (ResBGNets), to improve the accuracy of moving objects detection in video sequences. Instead of learning the ground truth directly, our model learns the residual pictures between the results of existing methods and the ground truth. It benefits to understand the hidden character of each algorithm and correct the misclassification. Inside ResBGNets, we build Feature Pyramid Networks (FPN) to combine spatial information of the low-resolution level with semantical features of high-level of the high-resolution level. Evaluation performed on the 2014 CDnet dataset reveals that through our approach, most of the existing background subtraction methods can get better detection results and a significant higher FM score.

关键词： Moving objects detection convolutional neural networks background subtraction residual pictures feature pyramids

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parallel and Distributed Visualization the State of the Art

Parallel and Distributed Visualization The State of the Art

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5th international conference on Computer Graphics, Imaging and Visualization (CGIV)

作者： Meligy, Ali Middle E Univ Grad Studies Fac Informat Technol Amman Jordan

ISBN: (纸本)9780769533599

Visualization is one of the most important applications of computer graphics. To have a parallel infrastructure for visualization, some technologies would be needed. We identify the state-of-the-art technologies that have prepared for building such an infrastructure and examine a collection of applications that would benefit from it. We consider a broad range of scientific and technological advances in visualization, which are relevant to visual supercomputing. Mainly, we present the original abstracts from the cited papers.

关键词： parallel processing distributed processing cluster computers parallel rendering algorithms visual supercomputing visualization autonomic computing mobile visualization

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parallel Stateful Logic in RRAM: theoretical Analysis and Arithmetic Design 30

Parallel Stateful Logic in RRAM: Theoretical Analysis and Ar...

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30th IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Wang, Feng Luo, Guojie Sun, Guangyu Zhang, Jiaxi Huang, Peng Kang, Jinfeng Peking Univ Ctr Energy Efficient Comp & Applicat Beijing Peoples R China Peking Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781728116013

processing-in-memory (PIM) provides massive parallelism with high energy efficiency and becomes a promising solution to the "memory wall" problem. Recently, the emerging metal-oxide resistive random access memory (RRAM) has shown its potential to design a PIM architecture. Several stateful logic operations, e.g., NOR and NAND, can be executed in parallel in an RRAM crossbar. Although previous works have designed some algorithms using the stateful logic, it is still under exploration how to fully exploit its potential high parallelism and design an asymptotically fast algorithm for a given function. In this work, we theoretically analyze the parallelism in an RRAM crossbar and design several asymptotically optimal arithmetic algorithms. In detail, we first propose the Single Instruction Multiple Lines (SIML) model to unify the stateful logic families and prove three lower bounds on the time complexity of a parallel RRAM algorithm. then, we design three algorithms for integer addition functions with the stateful logic, guided by the lower bound analysis. All of them reach the time complexity lower bound. Finally, We make two extensions of the integer addition algorithms, supporting multiplication functions by decomposing them to additions and supporting the flex-point data type by proposing an exponent and mantissa update flow. Experimental evaluation shows that our integer algorithms achieves a speedup up to 13.79x over the previous RRAM algorithms. Our flex-point implementation achieves a 26.60x speedup and saves 73.68% energy compared to an ARM.

关键词： Time complexity Computer architecture parallel processing Computational modeling Resistance Switches Random access memory

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parallel algorithms for the Weighted Distance Transform on Linear Arrays with a Reconfigurable Pipelined Bus System

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9th international conference on algorithms and architectures for parallel processing

作者： Tsai, Horng-Ren Ling Tung Univ Dept Informat Technol Taichung Taiwan

ISBN: (纸本)9783642030949

In this paper, based on the advantages of both optical transmission and electronic computation, we first provide an O(log log N) bus cycles parallel algorithm for weighted distance transforms of an NxN binary image on a linear array with a reconfigurable pipelined bus System using N-2 processors. By increasing the number of processors, the proposed algorithm can be run in O(loglog(q) N) and O(l) bus cycles using qN(2) and N2+1/epsilon processors respectively, where 2 <= q <= root N, epsilon is a constant and epsilon >= 1. these results improve on previously known algorithms developed on various parallel computation models.

关键词： Distance transform image processing parallel algorithms linear array with a reconfigurable pipelined bus system

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parallel Symbolic Observation Graph 15

Parallel Symbolic Observation Graph

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15th IEEE international Symposium on parallel and Distributed processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Ouni, Hiba Klai, Kais Abid, Chiheb Ameur Zouari, Belhassen Univ Tunis El Manar Fac Sci Tunis Tunis 2092 Tunisia Univ Carthage Higher Sch Commun Tunis Mediatron Lab Tunis Tunisia Univ Paris 13 Sorbonne Paris Cite CNRS UMR 7030 LIPN Villetaneuse France

ISBN: (纸本)9781538637906

Model checking is a powerful technique for verifying and analyzing complex systems in many application fields. the analysis process of complex and concurrent systems often requires large computation resources which represents a real challenge. Even with simple configurations, the well-known state explosion problem is faced as the generated state space of such systems grows exponentially with the number of the system components. Numerous methods and techniques have been developed to overcome this problem including parallel and distributed-memory processing. In this paper, we aim at improving the performances of the so called Symbolic Observation Graph (SOG) construction by using parallelization techniques. A SOG is a hybrid structure where the transitions of a system are divided into observed and unobserved ones. the nodes of this graph are then defined as sets of states linked with unobserved transitions (and encoded symbolically with a BDD) and edges are labeled with observed transitions only (and are explicitly represented). We propose two parallel algorithms to build the SOG. the first algorithm is dedicated for shared memory architectures, and is based on the distribution of the SOG construction on several threads using a dynamic load balancing scheme. the second algorithm is proposed for distributed memory architectures, and distributes the SOG construction on processes using a static load balancing scheme. these two algorithms are implemented and their performances are studied and compared to each other and to the sequential construction of the SOG.

关键词： Distributed memory Multi threading parallel model checking Symbolic reachability

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