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IEEE international conference on High Speed Networks and Multimedia Communications

作者： Myoung-Soo Kang Yoon-Chul Choy Department of Computer Science Yonsei University Seoul South Korea

there have been a need for accessing spatial data from distributed and preexisting spatial database systems interconnected through a network. In a distributed environment, spatial joins for two spatial relations residing at geographically separated sites are expensive in terms of computation and transmission cost because of the large size and complexity of spatial data. therefore, we propose a new spatial join method for distributed spatial databases. Previously, a distributed algorithm based on the spatial semijoin has accomplished performance improvements by eliminating objects before transmission to reduce both transmission and local processing costs. But with widespread high bandwidth data transmission, parallelism through data redistribution may improve the performance of spatial joins in spite of additional transmission costs. Hence, we propose a parallel spatial join processing that combines the data-partitioning techniques used by most parallel join algorithms in relational databases and the filter-and-refinement strategy for spatial operation processing for distributed spatial databases. In experiments, we showed that the proposed method provides useful reductions in the cost of evaluating a join.

关键词： Costs Distributed databases Spatial databases Relational databases Database systems Distributed computing Computational efficiency Distributed algorithms Bandwidth Data communication

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parallelizing the data cube 1

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8th international conference on Database theory (ICDT 2001)

作者： Dehne, F Eavis, T Hambrusch, S Rau-Chaplin, A Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada Dalhousie Univ Fac Comp Sci Halifax NS B3H 1W5 Canada Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

ISBN: (数字)9783540445036

ISBN: (纸本)9783540414568

this paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one for top-down and one for bottom-up cube algorithms. Both partitioning strategies assign subcubes to individual processors in such a way that the loads assigned to the processors are balanced. Our methods reduce inter processor communication overhead by partitioning the load in advance instead of computing each individual group-by in parallel. Our partitioning strategies create a small number of coarse tasks. this allows for sharing of prefixes and sort orders between different group-by computations. Our methods enable code reuse by permitting the use of existing sequential (external memory) data cube algorithms for the subcube computations on each processor. this supports the transfer of optimized sequential data cube code to a parallel setting. the bottom-up partitioning strategy balances the number of single attribute external memory sorts made by each processor. the top-down strategy partitions a weighted tree in which weights reflect algorithm specific cost measures like estimated group-by sizes. Both partitioning approaches can be implemented on any shared disk type parallel machine composed of p processors connected via an interconnection fabric and with access to a shared parallel disk array. We have implemented our parallel top-down data cube construction method in C++ with the MPI message passing library for communication and the LEDA library for the required graph algorithms. We tested our code on an eight processor cluster, using a variety of different data sets with a range of sizes, dimensions, density, and skew. Comparison tests were performed on a SunFire 6800. the tests show that our partitioning strategies generate a close to optimal load balance between processors. the actual run times observed show an optimal speedup of p.

关键词： OLAP data cube parallel processing partitioning load balancing

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A parallel spatial join processing for distributed spatial databases 1

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5th international conference on Flexible Query Answering Systems, FQAS 2002

作者： Kang, Myoung-Soo Ko, Seung-Kyu Koh, Kyun Choy, Yoon-Chul Department of Computer Science Yonsei University 134 Seoul 120-749 Korea Republic of Department of Computer and Information Engineering Chongju University Cheongju Chungbuk 360-764 Korea Republic of

ISBN: (数字)9783540361091

ISBN: (纸本)3540000747

In recent years, there have been needs of accessing spatial data from distributed and preexisting spatial database systems interconnected through a network. In a distributed environment, spatial joins for two spatial relations residing at geographically separated sites are expensive in terms of computation and transmission cost because of the large size and complexity of spatial data. Previous distributed algorithm based on the spatial semijoin has accomplished performance improvements by eliminating objects before transmission to reduce both transmission and local processing costs. But with a widespread of a high bandwidth data transmission, the parallelism through data redistribution may improve the performance of spatial joins in spite of additional transmission costs. Hence, we propose a parallel spatial join processing for distributed spatial databases. We apply the task distribution method minimizing the data transmission and the solution for task distribution using a graph partitioning method. In experiments, we showed that the proposed method provides useful reductions in the cost of evaluating a join. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Cost reduction

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Exploiting the prefetching effect provided by executing mispredicted load instructions 8th

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8th international Euro-Par conference on parallel processing, Euro-Par 2002

作者： Sendag, Resit Lilja, David J. Kunkel, Steven R. Department of Electrical and Computer Engineering Minnesota Supercomputing Institute University of Minnesota 200 Union St. S.E MinneapolisMN55455 United States IBM RochesterMN United States

ISBN: (纸本)3540440496

As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. this wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor. © Springer-Verlag Berlin Heidelberg 2002.

关键词： parallel processing systems

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Coordination models and languages : 5th international conference, COORDINATION 2002, York, UK, April

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2002年

作者： Coordination 2002

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Recursive filters using systolic architectures and switched capacitor techniques

Recursive filters using systolic architectures and switched ...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Chikouche R.E. Bekka A. Boucenna Département d Electronique Faculté des Sciences de IIngénieur Université de Satif Setif Algeria

In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to realize recursive filters of 1D and 2D types. We show that the recursivity inherent to the filtering algorithm introduces a latency proportional to the filter order. Moreover, we show that the use of the CTP decomposition technique together with the cylindrical-type structures reduces significantly this latency and improves the computation throughput of these arrays. the processing cells of the systolic array are designed via switched-capacitor techniques.

关键词： Filters Capacitors State-space methods Computer architecture throughput Equations Filtering algorithms Delay Systolic arrays Process design

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Fast software implementation of MPEG advanced audio encoder

Fast software implementation of MPEG advanced audio encoder

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international conference on Digital Signal processing (DSP)

作者： I. Dimkoviae D. Milovanoviae Z. Bojkoviae PsyTEL Research Belgrade Serbia Faculty of Elcclrical Engineering Belgrade Serbia

An optimized software implementation of a high quality MPEG AAC-LC (low complexity) audio encoder is presented in this paper. the standard reference encoder is improved by utilizing several algorithmic optimizations (fast psycho-acoustic model, new tonality estimation, new time domain block switching, optimized quantizer and Huffman coder) and very careful code optimizations for PC CPU architectures with SIMD (single-instruction-multiple-data) instruction set. the psychoacoustic model used the MDCT filterbank for energy estimation and peak detection as a measure of tonality. Block size decision is based on local perceptual entropies as well as LPC analysis of the time signal. Algorithmic optimizations in the quantizer include loop control module modification and optimized Huffman search. Code optimization is based on parallel processing by replacing vector algebra and math junctions with their optimized equivalents with Intel/sup /spl reg// Signal processing Library (SPL). the implemented codec outperforms consumer MP3 encoders at 30% less bitrate at the same time achieving encoding times several times faster than real-time.

关键词： Signal processing algorithms Psychoacoustic models Software quality Code standards Psychology Filter bank Energy measurement Entropy Linear predictive coding Signal analysis

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Analogic cellular PDE machines

Analogic cellular PDE machines

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international Joint conference on Neural Networks (IJCNN)

作者： C. Rekeczky I. Szatmari P. Foldesy T. Roska Computer and Automation Research Institute Hungary Hungarian Academy of Science Budapest Hungary Jedlik Laboratories Department of Information Technology Pázmány Péter Catholic University Budapest Hungary

this paper gives an overview on analogic cellular array architectures that can also be used to approximate partial differential equations (PDEs). Cellular arrays are massively parallel computing structures composed of cells placed on a regular grid. these cells interact locally an th e array can have both local and global dynamics. the software of this architecture is an analogic algorithm that builds on analog and logical spatio-temporal instructions of the underlying hardware, that is a locally connected cellular nonlinear network (CNN). Within this framework two classes of PDEs, motivated also by image processing methodologies will be discussed: (i) reaction-diffusion (local) types and (ii) contrast modification (global) types. It will be shown that based on cellular diffusion and wave-computing formulations these classes can be approximated on existing CNN Universal Machine (CNN-UM) chips. thus, the last generation of stored program topographic array microprocessors with integrated sensing and computing could also be viewed as the first prototypes of analogic cellular PDE machines implemented on silicon.

关键词： Computer architecture Cellular neural networks Partial differential equations parallel processing Software algorithms Hardware Cellular networks Image processing Turing machines Microprocessors

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Laser and vision sensing for road detection and reconstruction

Laser and vision sensing for road detection and reconstructi...

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international conference on Intelligent Transportation

作者： W.S. Wijesoma K.R.S. Kodagoda A.P. Balasuriya School of Electrical and Electronic Engineering Nanyang Technological University Singapore

In most urban roads, and similar environments such as in theme parks, campus sites, industrial estates, science parks and the like, the painted lane markings that exist may not be easily discernible by CCD cameras due to poor lighting, bad weather conditions, and inadequate maintenance. An important feature of roads in such environments is the existence of pavements or curbs on either side defining the road boundaries. these curbs, which are mostly parallel to the road, can be harnessed to extract useful features of the road for implementing autonomous navigation or driver assistance systems. However, extraction of the curb or road edge feature using vision image data is a very formidable task as the curb is not conspicuous in the vision image. To extract the curb using vision data requires extensive image processing, heuristics and very favorable ambient lighting. In our approach, the curb data is extracted speedily rising range data provided by a 2D laser range measuring device. this information is then used to extract the mid-line(s) in the vision image using an extended Kalman filtering approach. Subsequently, midline data is used for the prediction of the road boundaries. Experimental results are presented to demonstrate the viability and effectiveness of the proposed methodology.

关键词： Roads Data mining Laser theory Image reconstruction Charge coupled devices Charge-coupled image sensors Feature extraction Navigation Image processing Velocity measurement

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parallel explicit finite element dynamics with nonlocal constitutive models

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COMPUTERS & STRUCTURES 2001年第26-28期79卷 2287-2297页

作者： Patzák, B Rypl, D Bittnar, Z Czech Tech Univ Fac Civil Engn Prague 16629 Czech Republic

the present paper deals with the parallelization of an explicit time stepping algorithm in a general finite element environment. Particular attention has been paid to nonlocal constitutive models. A central difference method has been used to discretize the governing equations in time. Modifications of both node-cut and element-cut strategies have been developed to provide an efficient support for nonlocal constitutive models. Efficiency of the proposed approach is demonstrated on different hardware platforms. (C) 2001 Civil-Comp Ltd. and Elsevier Science Ltd. All rights reserved.

关键词： parallel processing explicit dynamics nonlocal models

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