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7th European conference on parallel Computing, Euro-Par 2001

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7th European conference on parallel Computing, Euro-Par 2001

ISBN: (纸本)3540424954

the proceedings contain 130 papers. the special focus in this conference is on parallel processing. the topics include: Software component technology for high performance parallel and grid computing;connecting computational requirements with computing resources;a tool for binding to threads processors;a distributed object infrastructure for interaction and steering;optimal polling for latency-throughput tradeoffs in queue-based network interfaces for clusters;performance prediction of data-dependent task parallel programs;the hardware performance monitor toolkit;via communication performance on a gigabit Ethernet cluster;group-based performance analysis for multithreaded SMP cluster applications;exploiting unused time slots in list scheduling considering communication contention;an evaluation of partitioners for parallel SAMR applications;load balancing on networks with dynamically changing topology;approximation algorithms for scheduling independent malleable tasks;load redundancy elimination on executable code;using a swap instruction to coalesce loads and stores;data-parallel compiler support for multipartitioning;parallel and distributed databases, data mining and knowledge discovery;an experimental performance evaluation of join algorithms for parallel object databases;a classification of skew effects in parallel database systems;experiments in parallel clustering with DBSCAN;analysis of the cycle structure of permutations;scanning biosequence databases on a hybrid parallel architecture;experiences in using MPI-Io on top of GPFS for the IFS weather forecast code;improving conditional branch prediction on speculative multithreading architectures;performances of a dynamic threads scheduler and self-stabilizing neighborhood unique naming under unfair scheduler.

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parallel pruning for k-means clustering on shared memory architectures 7

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7th European conference on parallel Computing, Euro-Par 2001

作者： Gürsoy, Attila Cengiz, İlker Computer Engineering Department Bilkent University Ankara Turkey

ISBN: (纸本)3540424954

We have developed and evaluated two parallelization schemes for a tree-based k-means clustering method on shared memory machines. One scheme is to partition the pattern space across processors. We have determined that spatial decomposition of patterns outperforms random decomposition even though random decomposition has almost no load imbalance problem. the other scheme is the parallel traverse of the search tree. this approach solves the load imbalance problem and performs slightly better than the spatial decomposition, but the efficiency is reduced due to thread synchronizations. In both cases, parallel treebased k-means clustering is significantly faster than the direct parallel k-means. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Clustering algorithms

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Pipelined hash joins using network of workstations 14

Pipelined hash joins using network of workstations

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14th international conference on parallel and Distributed Computing Systems

作者： Jalali, S Dandamudi, S Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada

ISBN: (纸本)1880843390

A network of workstations is a cost-effective alternative to parallel database systems. this paper studies the performance of hash join operations on a Pentium-based network of workstations platform. Specifically, we study performance of intraquery (pipelined) and intra-operation (partitioned) parallelism in a centralized query processing architecture. We also study the impact of the network bandwidth on the performance of the join algorithms. For this purpose, in our experimental study, we use a 10 Mbps Ethernet and a 100 Mbit fast Ethernet. Our performance results suggest that pipelined hash joins exhibit significant improvement in response time for complex queries and for queries that involve large input relations.

关键词： Query processing

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Digital signal processing system for image pattern recognition

Digital signal processing system for image pattern recogniti...

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international conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service (TELSIKS)

作者： S. Zoican Electronic and Telecommunication Faculty Telecommunication Department POLITEHNICA University of Bucharest Bucharest Romania

this paper evaluates the possibility of using a digital signal processor (DSP) in order to implement an image pattern recognition system based on a neural network architecture. the paper presents a brief introduction to neural network architectures and how such architectures can be used in pattern recognition; it presents the implementation of the neural network using a very powerful DSP microcomputer (eg, ADSP 2189 from Analog Devices), illustrates the main results for a character recognition system (execution time and error probability), and presents some conclusions.

关键词： Digital signal processing Pattern recognition Neural networks Signal processing algorithms Microcomputers Image recognition Digital signal processors Error probability Image databases Pixel

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Digital signal processing system for image pattern recognition

Digital signal processing system for image pattern recogniti...

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5th international conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service

作者： Zoican, S Politehnica Univ Elect & Telecommun Fac Telecommun Dept Bucharest 77202 Romania

ISBN: (纸本)078037228X

this paper evaluates the possibility to use a Digital Signal Processor (DSP) in order to implement an image pattern recognition system based on neural network architecture. the paper is organized as follows: section I represent a brief introduction in neural networks architectures and how such architecture can be used in pattern recognition, section 11 present the implementation of the neural network using a very powerful DSP microcomputer (e.g. ADSP 2189 from Analog Devices), section III illustrated the main results for a letters recognition system (execution time and error probability) and section IV represents the conclusions.

关键词： DSP algorithm DSP microcomputer neural network architecture

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Web mining is parallel 8th

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8th international conference on High Performance Computing, HiPC 2001

作者： Kitsuregawa, Masaru Pramudiono, Iko Takahashi, Katsumi Prasetyo, Bowo Institute of Industrial Science University of Tokyo 4-6-1 Komaba Meguro-ku Tokyo153-8505 Japan

ISBN: (纸本)3540430091

the emerging WWW poses new technological challenges for information processing. the scale of WWW is expected to keep growing as more devices, such as mobile phones and PDAs are equipped with the ability to access internet. Here we report the application of data mining techniques on large scale web data of a directory service for users of i- Mode, a major mobile phone internet access in Japan. We develop tool to visualize the behavior of web site visitors. We also report experiments on PC cluster as promising platform for large scale web mining. parallel algorithms for generalized association rules are implemented on PC cluster with 100 PCs. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Microcomputers

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Realization of an airborne radar parallel signal processing system

Realization of an airborne radar parallel signal processing ...

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IEEE international conference on Radar

作者： Xu Junyi Wang Xiutan Peng Yingning Department of Electronic Engineering Tsinghua University Beijing China

ISBN: (纸本)0780370007

In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. the DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar.

关键词： Airborne radar Radar signal processing Digital signal processing chips Real time systems Clutter Object detection Control systems Kernel parallel architectures parallel processing

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Real time skin-region detection with a single-chip digital camera

Real time skin-region detection with a single-chip digital c...

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IEEE international conference on Image processing

作者： R. Kleihorst Mi-Suen Lee A. Abbo E. Cohen-Solal Philips Research Laboratories Eindhoven Netherlands Philips Research Laboratories Briarcliff Manor NY USA

this article describes a 30 frames/second VGA format image sensor made in a standard CMOS process with an embedded massively parallel processor. the processor is fully programmable and therefore the sensor IC itself is able to run a variety of algorithms with data and processing in close vicinity of the sensor. Because of the parallel architecture comprising processor array and parallel memory accesses, high computational performances of up to 5 GOPS at 16 MHz are achieved. this high performance allowed us to implement skin tone detection on the camera itself as part of a larger system for face recognition, releasing the host computer of cumbersome pixel processing tasks and minimizing the data transfer between camera and computer.

关键词： Digital cameras Energy consumption Laboratories parallel architectures High performance computing Skin Computer architecture Process control Communication system control Color

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Comparing and combining read miss clustering and software prefetching

Comparing and combining read miss clustering and software pr...

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international conference on parallel Architecture and Compilation Techniques (PACT)

作者： V.S. Pai S.V. Adve Electrical and Computer Engineering Rice University Houston TX USA Computer Science University of Illinois Urbana-Champaign IL USA

A recent latency tolerance technique, read-miss clustering, restructures code to send demand-miss references in parallel to the underlying memory system. An alternative, widely-used latency tolerance technique is software prefetching, which initiates data fetches ahead of expected demand-miss references by a certain distance. Since both techniques seem to target the same types of latencies and use the same system resources, it is unclear which technique is superior or if both can be combined. this paper shows that these two techniques are actually mutually beneficial, each helping to overcome limitations of the other: We perform our study for uniprocessor and multiprocessor configurations, in simulation and on a real machine (the Convex Exemplar). Compared to prefetching alone (the state-of-the-art implemented in systems today), the combination of the two techniques reduces the execution time by an average of 21% across all cases studied in simulation, and by an average of 16% for 5 out of 10 cases on the Exemplar. the combination sees execution time reductions relative to clustering alone averaging 15% for 6 out of 11 cases in simulation and 20% for 6 out of 10 cases on the Exemplar.

关键词： Prefetching Delay parallel processing Out of order Pipeline processing Hardware Concurrent computing Computer science Software algorithms Steady-state

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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

VLSI-based parallel architecture for block-matching motion e...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Donglai Xu J. Bentley School of Science and Technology University of Teesside Middlesbrough UK

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

关键词： parallel architectures Motion estimation Video coding Computer architecture Very large scale integration Field programmable gate arrays Circuits Costs Pipelines Silicon

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