A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit's core as smart pixel detector chip is presented. this architecture is well-suited for a realization with 3-D...
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ISBN:
(纸本)0818685727
A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit's core as smart pixel detector chip is presented. this architecture is well-suited for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. this allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. this is demonstrated for a pipelined arithmetic unit using a redundant number representation. A gate layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technolgy.
this paper presents algorithms and architectures for implementing from 1-D to multidimensional M-D digital nonrecursive filters. these architectures are very regular and support single chip implementation in VLSI, as ...
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An overview on VLSI architectures for multimedia processing is given. Dedicated as well as programmable approaches are discussed. Dedicated implementations are derived utilizing specific properties of the target algor...
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this paper describes an insertion opportunity for optical interconnection technology in embedded massively parallel processors for radar signal processing.
ISBN:
(纸本)0818685727
this paper describes an insertion opportunity for optical interconnection technology in embedded massively parallel processors for radar signal processing.
this paper proposes a new compile time scheduling algorithm for distributed-memory systems, called Global Load Balancing (GLB). GLB is intended as the second step in the multi-seep class of scheduling algorithms. Expe...
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ISBN:
(纸本)0818691948
this paper proposes a new compile time scheduling algorithm for distributed-memory systems, called Global Load Balancing (GLB). GLB is intended as the second step in the multi-seep class of scheduling algorithms. Experimental results show that compared with known scheduling algorithms of the same low-cost complexity, the proposed algorithm improves schedule lengths lip to 30%. Compared to algorithms with higher order complexities, the typical schedule lengths obtained withthe proposed algorithm are at most twice longer.
Emerging trends in computer design attempt to include specific solutions for handling images also in general-purpose computers, because of the current spread of multimedia, image processing and computer graphics appli...
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ISBN:
(纸本)0818691948
Emerging trends in computer design attempt to include specific solutions for handling images also in general-purpose computers, because of the current spread of multimedia, image processing and computer graphics applications. In this context, this paper proposes hardware pre-fetching techniques specific for caching images: the main issue we state is that most algorithms working opt images exhibit a 2D spatial locality that is not taken into account in current cache organization and data access strategies. To this aim we propose an adaptive local pre-fetching for the image data type;this technique, mirroring the two-dimensional spatial locality of image processingalgorithms, results to be more efficient than other approaches, such as sequential pre-fetching and adaptive pre-fetching. Performance is evaluated on different classes of image processingalgorithms, namely raster-scan and propagative algorithms, common in computer vision and multimedia applications.
the parallel model combination (PMC) technique has been shown to achieve very good performance for speech recognition under noisy conditions. However, there still exist some problems based on the PMC formula. In this ...
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We present a smart pixel device for networking and parallelprocessing based on the use two-dimensional arrays optical channels between VLSI chip planes.
ISBN:
(纸本)0818685727
We present a smart pixel device for networking and parallelprocessing based on the use two-dimensional arrays optical channels between VLSI chip planes.
In a complete directed weighted graph there are jobs located at nodes of the graph. Job i has an associated processing time or handling time h(i), and the job must start within a prespecified time window [r(i), d(i)]....
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ISBN:
(纸本)0818691948
In a complete directed weighted graph there are jobs located at nodes of the graph. Job i has an associated processing time or handling time h(i), and the job must start within a prespecified time window [r(i), d(i)]. A vehicle can move on the arcs of the graph, at unit speed, and that has to execute the jobs within their respective time windows. We consider three different problems on the CREW PRAM. (1) Find the minimum cost routes between all pairs of nodes in a network. We give an O(log(3) n) time algorithm with n(4)/log(2) n processors. (2) Services all locations in minimum time. the general problem is NP-complete but O(n(2)) time algorithms are known for a special case;for this case we obtain an O(log(3) n) time parallel algorithm using n(4)/log(2) n processors and a linear time optimal parallel algorithm. (3) Minimize the sum of waiting times at all locations. the general problem is NP-complete but O(n(2)) time algorithm are known for a special case;for this case, we obtain an O(log(2) n) time algorithm with n(3)/log n processors and also a linear time optimal parallel algorithm.
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