An overview on VLSI architectures for multimedia processing is given. Dedicated as well as programmable approaches are discussed. Dedicated implementations are derived utilizing specific properties of the target algor...
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An overview on VLSI architectures for multimedia processing is given. Dedicated as well as programmable approaches are discussed. Dedicated implementations are derived utilizing specific properties of the target algorithms. For programmable processors, a number of architectural measures to increase multimedia processing performance are identified, and design examples of existing processors are reviewed. Future trends in multimedia signal processing and their implications on VLSI architecture design are anticipated.
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an inte...
ISBN:
(纸本)0780350081
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an interval method for global non-linear DC analysis;an analysis method for the performance comparison of communication systems;high performance interconnection architecture for large cellular neural networks;spice simulations of DC electrothermal interactions in bipolar electronic circuits;retrieval of butterfly from its sketched image utilizing image navigation directory on multimedia network;a continuous-time area detector servo demodulator for hard disk drives;a simplification before and during generation methodology for symbolic large-circuit analysis;a very-long instruction word digital signal processor based on the logarithmic number system;design techniques for highly efficient class-F amplifiers driven by low voltage supplies;and symbolic synthesis of analog-to-digital conversion architectures using direct mapping techniques.
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an inte...
ISBN:
(纸本)0780350081
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an interval method for global non-linear DC analysis;an analysis method for the performance comparison of communication systems;high performance interconnection architecture for large cellular neural networks;spice simulations of DC electrothermal interactions in bipolar electronic circuits;retrieval of butterfly from its sketched image utilizing image navigation directory on multimedia network;a continuous-time area detector servo demodulator for hard disk drives;a simplification before and during generation methodology for symbolic large-circuit analysis;a very-long instruction word digital signal processor based on the logarithmic number system;design techniques for highly efficient class-F amplifiers driven by low voltage supplies;and symbolic synthesis of analog-to-digital conversion architectures using direct mapping techniques.
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an inte...
ISBN:
(纸本)0780350081
the proceedings contain 363 papers. the topics discussed include: high-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications;a linear programming implementation of an interval method for global non-linear DC analysis;an analysis method for the performance comparison of communication systems;high performance interconnection architecture for large cellular neural networks;spice simulations of DC electrothermal interactions in bipolar electronic circuits;retrieval of butterfly from its sketched image utilizing image navigation directory on multimedia network;a continuous-time area detector servo demodulator for hard disk drives;a simplification before and during generation methodology for symbolic large-circuit analysis;a very-long instruction word digital signal processor based on the logarithmic number system;design techniques for highly efficient class-F amplifiers driven by low voltage supplies;and symbolic synthesis of analog-to-digital conversion architectures using direct mapping techniques.
A continuous-time analog median filter implementation is presented. the filter uses two new circuits to implement the delay line and median blocks. Both circuits were designed a compact and modular structure to allow ...
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In this paper we present Semi-bit-serial and programmable circuit architectures for performing arithmetic in GF (2m). the semi-bit-serial mathematical architectures offer a structure that operates faster than traditio...
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In this paper we present Semi-bit-serial and programmable circuit architectures for performing arithmetic in GF (2m). the semi-bit-serial mathematical architectures offer a structure that operates faster than traditional bit-serial architectures, whilst offering considerably lower hardware requirements than a bit-parallel architecture. this new approach to arithmetic operations in GF (2m) is based on composite fields of the form GF((2n)2) (m = 2n) . It is also shown that these operators lend themselves to programmable architecturesthat operate in either GF(2m) or GF(2n). the circuit architectures proposed in this paper support implementation in VLSI systems due to their regular and hardware efficient circuit structures and are therefore suited to use in Reed-Solomon error-correction codecs.
Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. this paper presen...
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Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. this paper presents a new FPGA architecture suitable for the application specific signal processingalgorithms and Wafer-Scale integration (WSI) Technology. the architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. the proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. the architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture. the design methodology, the design tools, and results obtained by using a Segmented Channel Routing algorithm to map on it a 16 bit parallel multiplier, are presented.
the paper deals with a prototype digital hardware architecture implementing a `Cellular Fuzzy processing (CFP)' array. the powerful collective behavior of such systems derives basically from the ability to specify...
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the paper deals with a prototype digital hardware architecture implementing a `Cellular Fuzzy processing (CFP)' array. the powerful collective behavior of such systems derives basically from the ability to specify their dynamics only within the scope of a single cell and of the nearest neighboring cells. Some off-line simulation demonstrates the capability to reproduce a wide set of complex phenomena such as patterns formation, spiral waves and auto-waves dynamics, self-organization phenomena, and PDE numerical solving.
A continuous-time analog median filter implementation is presented. the filter uses two new circuits to implement the delay line and median blocks. Both circuits were designed a compact and modular structure to allow ...
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A continuous-time analog median filter implementation is presented. the filter uses two new circuits to implement the delay line and median blocks. Both circuits were designed a compact and modular structure to allow implementation of array processors. In addition, a novel technique for image processing is presented. the circuit was designed for a 2 μm technology MOSIS process.
this paper presents the architecture of a high-speed Digital Signal Processor (DSP) designed for high rate digital modem applications. this work stands as a part of an EURICO European project, whose target is the desi...
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this paper presents the architecture of a high-speed Digital Signal Processor (DSP) designed for high rate digital modem applications. this work stands as a part of an EURICO European project, whose target is the design of a TV cable modem. First, some aspects of the TV cable digital modem application are presented. then, the paper describes the DSP architecture, based on a VLIW core processor and on Auxiliary Dedicated Modules (ADM). the architectural choices and the main advantages are discussed. Last, the general structure of the ADMs is discussed through an example: the implementation of a Cyclic Redondancy Checking (CRC) dedicated ADM.
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