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Scheduling algorithms for parallel transaction processing systems 4th

Scheduling algorithms for parallel transaction processing sy...

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4th international conference on parallel Computing Technologies, PaCT 1997

作者： Wang, Jiahong Li, Jie Kameda, Hisao Institute of Information Sciences and Electronics University of Tsukuba Tsukuba Science CityIbaraki305 Japan

ISBN: (纸本)3540633715

Shared-nothing parallel transaction processing (TP) systems have great potential to serve the ever-increasing demands for high transaction processing rate. this potential, however, may not be reached due to the negative effect of the widely used two-phase locking (2PL) concurrency control method. We observed that for the shared-nothing parallel TP system, this negative effect of 2PL can be alleviated significantly by scheduling transactions judiciously. In this paper, a new transaction scheduling algorithm called FCFSP (FCFS with Priority) is proposed thereby. In order to study the performance of transaction scheduling algorithms, a comprehensive simulator for shared-nothing parallel TP systems is developed. Using the developed simulator, the performance of FCFSP is compared with that of the conventional FCFS and the previously proposed SCST (Synchronizing Completion of SubTransactions) transaction scheduling algorithms. Simulation results demonstrate the effectiveness of FCFSP. Simulation results also show that FCFSP outperforms FCFS greatly, and overcomes the drawback of SCST. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Scheduling algorithms

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Memory-optimized visualization system for limited-bandwidth multiprocessing environments

Memory-optimized visualization system for limited-bandwidth ...

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Proceedings of the 1997 4th international conference on High Performance Computing, HiPC

作者： Law, Asish Yagel, Roni Nichimen Graphics Inc Los Angeles United States

Object dataflow is a popular approach used in parallel rendering. the data representing the 3D scene is statically distributed among processors and objects are fetched and cached only on demand. Most previous object dataflow methods were implemented on shared memory architectures and exploited spatial coherency to reduce hardware cache misses. In this paper, we propose an efficient model for object dataflow parallel volume rendering on message passing machines. the algorithm is introduced and its ray storage mechanism is used to support latency hiding by postponing computation on inactive rays. Memory usage is optimized by letting objects migrate and replicate at different processors rather than the common static assignments. Our cache-only-memory approach uses a distributed-directory scheme to trace the location of objects at other nodes. A mechanism to minimize network congestion was implemented which optimizes channel utilization. Unlike previous methods, our approach can benefit from temporal coherence and effectively minimizes communication costs during animation on limited-bandwidth multiprocessing environments. We report results of the algorithm's implementation on several platforms like Cray T3D, Convex SPP and DEC-alpha cluster of workstations (COWs), and achieved higher efficiency and scalability than existing algorithms.

关键词： parallel processing systems

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Porting the chemical module of Calgrid code on a SIMD massively parallel platform

Porting the chemical module of Calgrid code on a SIMD massiv...

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Proceedings of the 1997 5th international conference on the Application of High-Performance Computers in Engineering, HPC

作者： Lorenzini, R. Monache, L.Delle Zanini, G. Cirillo, M.C. Celino, M. Palazzari, P. Italian Agency for New Technology Energy and Environment Roma Italy

the integration of stiff, very coupled, ordinary differential equations which describe pollutant chemical reactions is the most intensive computational task of photochemical models, since it requires at least 70% of the total CPU time. As a consequence of the local nature of these equations, the integration can be performed very efficiently by a SIMD architecture. In this work we present the porting of QSSA (Quasi Steady State Approximation) chemical solver of CALGRID photochemical model on the SIMD massively parallel platform Quadrics/APE100 which offers, in QH4 configuration, a peack performance of 25 Gflops.

关键词： parallel processing systems

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parallel implementation of the boundary element method using PVM and HPF on a collection of networked workstations

Parallel implementation of the boundary element method using...

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Proceedings of the 1997 5th international conference on the Application of High-Performance Computers in Engineering, HPC

作者： Mushtaq, J. Davies, A.J. Univ of Hertfordshire Hertfordshire United Kingdom

Solving large computationally intensive problems requires significant processing power and the current trend in achieving this power is not by increasing the throughput of individual processors, but to sub-divide the problem into co-operating tasks so that many processors may be used to solve the problem. Stand-alone workstations, such as the PC and the SUN machines, delivering tens of millions of operations per second are common place, but to achieve high parallel efficiency, distributed systems must support rapid communication between a large number of processors on a single coherent network. parallel programming packages have been developed to assist in parallel program development, such as the parallel Virtual Machine (PVM) and High Performance Fortran (HPF). In this paper we present an analysis of PVM and HPF within the context of the boundary element method. Domain decomposition is used to sub-divide and distribute a two-dimensional potential problem onto a collection of networked stand-alone workstations using PVM and HPF. We observe that the development of parallel applications using HPF is very efficient and straight forward when compared with PVM. However, PVM offers a better performance efficiency and a greater degree of freedom than HPF, since PVM allows both coarse and fine-grained parallelism. the performance of PVM and HPF are further compared with that of the 3L parallel Fortran on a T800 transputer network.

关键词： parallel processing systems

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Systematic design of 3-dimensional fixed-size array processors 4th

Systematic design of 3-dimensional fixed-size array processo...

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4th international conference on parallel Computing Technologies, PaCT 1997

作者： Likhoded, N.A. Tiountchik, A.A. Institute of Mathematics Academy of Sciences of Belarus Surganova str. 11 Minsk220072 Belarus

ISBN: (纸本)3540633715

A formalized method for a space-time mapping of algorithms onto three-dimensional fixed-size array processors without long interconnections is proposed. Initial algorithms are represented by dependence graphs which are constructed on the basis of recurrence equations. Some special forms of partitioning and spatial mapping of the graph models are considered to provide within the framework of locally parallel globally sequential strategy of partitioning both fixed size of the arrays and the locality of interconnections between processor elements. Conflict-free scheduling of the model is developed. Minimizing of the time requirements is considered. the parameters of scheduling providing the minimization are found. © Springer-Verlag Berlin Heidelberg 1997.

关键词： parallel processing systems

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A Tuple-based data structure for distributed parallel processing of 3D dynamic meshes 4th

A Tuple-based data structure for distributed parallel proces...

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4th international conference on parallel Computing Technologies, PaCT 1997

作者： Hartmann, Peter Fachbereich Informatik TH Darmstadt Alexanderstraβe 10 DarmstadtD-64283 Germany

ISBN: (纸本)3540633715

A data structure for the distributed representation of inhomogeneous and dynamically changing spatial structures is introduced. It is based on the concept of cellular hypergraphs (CHG), which provides us with a universal framework in this domain: a CHG is used to represent the topological relationships within a spatial structure, and the temporal dynamics are formulated with the productions of a parallel replacement system. the presented data structure is based on tuples keeping relationships between edges of the graph and components storing state information. A method for moving cells between processor nodes is described in detail, for it has a central meaning in load balancing algorithms and the distributed implementation of the parallel replacement systems. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Data structures

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Architecture design of motion estimation for ITU-T H.263

Architecture design of motion estimation for ITU-T H.263

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1997 conference on Visual Communications and Image processing

作者： Ku, CW Lin, GS Chen, LG Lee, YP National Taiwan Univ. (Taiwan)

ISBN: (纸本)0819424358

Digitalized video and audio system has become the trend of the progress in multimedia, because it provides great performance in quality and feasibility of processing. However, as the huge amount of information is needed while the bandwidth is limitted, data compression plays an important role in the system. Say, for a 176 x 144 monochromic sequence with 10 frames/sec frame rate, the bandwidth is about 2Mbps. this wastes much channel resource and limits the applications. MPEG (moving picttre ezpert groip) standardizes the video codec scheme, and it performs high compression ratio while providing good quality. MPEG-i is used for the frame size about 352 x 240 and 30 frames per second, and MPEG-2 provides scalibility and can be applied on scenes with higher definition, say HDTV (high definition television). On the other hand, some applications concerns the very low bit-rate, such as videophone and video-conferencing. Because the channel bandwidth is much limitted in telephone network, a very high compression ratio must be required. ITU-T announced the H.263 video coding standards to meet the above requirements.8 According to the simulation results of TMN-5,22 it outperforms 11.263 with little overhead of complexity. Since wireless communication is the trend in the near future, low power design of the video codec is an important issue for portable visual telephone. Motion estimation is the most computation consuming parts in the whole video codec. About 60% of the computation is spent on this parts for the encoder. Several architectures were proposed for efficient processing of block matching algorithms. In this paper, in order to meet the requirements of 11.263 and the expectation of low power consumption, a modified sandwich architecture in21 is proposed. Based on the parallel processing philosophy, low power is expected and the generation of either one motion vector or four motion vectors with half-pixel accuracy is achieved concurrently. In additi

关键词： Motion estimation Video Video compression Computer programming parallel processing Video coding Visualization Data compression Multimedia Video processing

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Optimal automatic hardware synthesis for signal processing algorithms

Optimal automatic hardware synthesis for signal processing a...

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international conference on Digital Signal processing (DSP)

作者： N. Koziris G. Economakos T. Andronikos G. Papakonstantinou P. Tsanakas Department of Electrical and Computer Engineering Computer Science Division National and Technical University of Athens Zografou Greece

this paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signal processing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit uniform loop carried dependencies. We model such algorithms with generalized UET grids. We calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required for achieving the optimal makespan. We present a complete methodology for the hardware synthesis of the resulting architecture, based on VHDL. this methodology automatically detects all necessary computation and communication elements and produces optimal layouts. the complexity of our proposed scheduling policy is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level signal processing algorithmic specifications to low-level (i.e., actual layouts) optimal implementation. the evaluation was performed using well-known algorithms from signal processing.

关键词： Hardware Signal synthesis Signal processing Signal processing algorithms Signal design Algorithm design and analysis Very large scale integration Digital signal processing Computer architecture Processor scheduling

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Compiler algorithms for optimizing locality and parallelism on shared and distributed memory machines

Compiler algorithms for optimizing locality and parallelism ...

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international conference on parallel Architecture and Compilation Techniques (PACT)

作者： M. Kandemir J. Ramanujam A. Choudhary EECS Department Syracuse University Syracuse NY USA Department of Electrical and Computer Engineering Louisiana State University Baton Rouge LA USA Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

Distributed memory message passing machines can deliver scalable performance but are difficult to program. Shared memory machines, on the other hand, are easier to program but obtaining scalable performance with a large number of processors is difficult. Previously, some scalable architectures based on logically-shared physically-distributed memory have been designed and implemented. While some of the performance issues like parallelism and locality are common to the different parallel architectures, issues such as data decomposition are unique to specific types of architectures. One of the most important challenges compiler writers face is to design compilation techniques that can work on a variety of architectures. In this paper, we propose an algorithm that can be employed by optimizing compilers for different types of parallel architectures. Our optimization algorithm does the following: (1) transforms loop nests such that, where possible, the outermost loops can be run in parallel across processors; (2) decomposes each array across processors; (3) optimizes interprocessor communication by vectorizing it whenever possible; and (it) optimizes locality (cache performance) by assigning appropriate storage layout for each array. Depending on the underlying hardware system, some or all of these steps can be applied in a unified framework. We present simulation results for cache miss rates, and empirical results on SUN SPARCstation 5, IBM SP-2, SGI Challenge and Convex Exemplar to validate the effectiveness of our approach on different architectures.

关键词： Optimizing compilers parallel processing Random access memory parallel machines Message passing parallel architectures Cache storage Hardware Sun Memory architecture

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Coming attractions in software architecture

Coming attractions in software architecture

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Workshop on parallel and Distributed Real-Time Systems

作者： P.C. Clements Software Engineering Institute Carnegie Mellon University Pittsburgh PA USA

Software architecture has emerged as an important topic in software engineering. this paper examines what is new about the subject, and what is not, and what research trends we may expect in the future. We discuss the promise that work in the field holds, and organize the work into five predominant themes: selection, representation, evaluation, development, and recovery. Technology for the formal representation of architectures is examined in detail, along with notions of architectural styles and patterns. the paper begins by examining the range of meanings associated with the term in order to provide a context for its treatment.

关键词： Software architecture Computer architecture Software engineering conference management Quality management Project management Software development management Engineering management Resonance Scheduling

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