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Communication and computation patterns of large scale image convolutions on parallel architectures

Communication and computation patterns of large scale image ...

引用

international Symposium on parallel processing

作者： S.G. Dykes Xiaodong Zhang Yan Zhou Haixu Yang High Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA

Segmentation and other image processing operations rely on convolution calculations with heavy computational and memory access demands. the article presents an analysis of a texture segmentation application containing a 96/spl times/96 convolution. Sequential execution required several hours an single processor systems with over 99% of the time spent performing the large convolution. 70% to 75% of execution time is attributable to cache misses within the convolution. We implemented the same application on CM-5, iPSC/860 and PVM distributed memory multicomputers, tailoring the parallel algorithms to each machine's architecture. parallelization significantly reduced execution time, taking 49 seconds on a 512 node CM-5 and 6.5 minutes on a 32 node iPSC/860. the results indicate for large kernel convolutions the size and bandwidth of the fast memory store is more important than processor power or communication overhead.< >

关键词： Concurrent computing Large-scale systems parallel architectures Image segmentation Image processing Kernel Laboratories Bandwidth Pixel Smoothing methods

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parallel processing for spatial grouping and matching

Parallel processing for spatial grouping and matching

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international conference on Pattern Recognition

作者： R. Nevatia C.C. Reinhart Institute for Robotics and Intelligent Systems University of Southern California Los Angeles CA USA Analog Image Processing Rockwell Science Center Inc. Thousand Oaks CA USA

In this paper, we identify the computational requirements for structural pattern analysis, particularly for the operations of spatial grouping and matching. We describe two such algorithms that are in wide use here at USC and discuss approaches to reducing their execution times via parallel implementation. We provide brief descriptions and results of two research projects geared generally, toward the parallel implementation of computer vision systems and specifically, towards these algorithms.

关键词： parallel processing Computer architecture Computer vision Intelligent robots Image edge detection Concurrent computing Hardware Software algorithms Intelligent systems Computational intelligence

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MULTISENSOR INTEGRATION USING NEURAL NETWORKS FOR PREDICTING QUALITY CHARACTERISTICS OF END-MILLED PARTS .1. INDIVIDUAL EFFECTS OF TRAINING PARAMETERS 5

MULTISENSOR INTEGRATION USING NEURAL NETWORKS FOR PREDICTING...

引用

5th international conference on Applications of Artificial Neural Networks

作者： OKAFOR, AC ADETONA, O UNIV MISSOURI DEPT MECH & AEROSP ENGN & ENGN MECHROLLAMO 65401

ISBN: (纸本)0819415472

this paper presents a systematic evaluation of the individual effects of training parameters: learning rate, momentum rate, number of hidden layer nodes, and processing element's transfer function, on the performance of back propagation networks in predicting quality characteristics of end milled parts. Multi-sensor signatures (acoustic emission, spindle vibration, and cutting force components) acquired during circular end-milling of 4140 steel and the corresponding measured quality characteristics (surface roughness and bore tolerance) were used to train the networks. the network is part of a proposed Intelligent Machining Monitoring and Diagnostic System for Quality Assurance of Machined Parts. the network performances were evaluated using four different criteria: maximum error, RMS error, mean error and number of training cycles. One of the results obtained shows that hyperbolic tangent transfer function gave a better performance than the sigmoid and sine functions respectively. Optimum combinations of training parameters have been observed. the effects of various combinations of training parameters are presented.

关键词： Neural networks Signal processing Manufacturing Sensors Surface roughness Diagnostics Network architectures Acoustic emission Artificial neural networks Tolerancing

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parallel scalable libraries and algorithms for computer vision

Parallel scalable libraries and algorithms for computer visi...

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international conference on Pattern Recognition

作者： L.H. Jamieson E.J. Delp S.E. Hambrusch A.A. Khokhar G.W. Cook F. Hameed J.N. Patel Ke Shem Purdue University West Lafayette IN USA Department of Computer Sciences Purdue University West Lafayette IN USA

We describe a project that integrates applications requirements, parallel algorithm design, models of parallel computing, and software tools in order to improve the ability of applications researchers in the fields of computer vision and image processing (CVIP) to realize the performance potential of high performance parallel computers. this objective is achieved by pursuing four directions of research: the development of efficient and practical scalable algorithms for fundamental CVIP problems; the implementation of realistic CVIP scenarios on high performance computers; the development of a scalable, architecture-independent parallel model and a metric for estimating the performance of an algorithm on an existing parallel machine; and the development of prototype software tools. In this paper we describe work in each of these areas.

关键词： Computer vision Application software Software tools Concurrent computing High performance computing Software algorithms Software libraries parallel algorithms Algorithm design and analysis parallel processing

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Distributed image edge detection methods and performance

Distributed image edge detection methods and performance

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international Symposium on parallel and Distributed processing (IPDPS)

作者： Xiaodong Zhang Hong Deng High-Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA

ISBN: (纸本)0818664274

An edge detection process in computer vision and image processing detects any types of significant features appearing as discontinuities in intensities. this paper presents our experience with parallelizing an edge detection application algorithm that reduces noise and unnecessary detail in a gray-scale image from a coarse level to a fine level of resolution by using an edge focusing technique. Numerical methods and parallel implementations of edge focusing are presented. the image detection algorithms are implemented on three representative message-passing architectures: a low-cost heterogeneous PVM network, an Intel iPSC/860 hypercube, and a CM-5 massively parallel multicomputer. Our objectives are to provide insight into implementation and performance issues for image processing applications on general-purpose message-passing architectures, to investigate implications an network variations, and to evaluate the computing scalabilities on the three network systems by examining execution and communication patterns of the image edge detection application.< >

关键词： Image edge detection Image processing Focusing Computer architecture Computer vision Application software Noise reduction Noise level Gray-scale Image resolution

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Evaluation and measurement of multiprocessor latency patterns

Evaluation and measurement of multiprocessor latency pattern...

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international Symposium on parallel processing

作者： Xiaodong Zhang Yong Yan Keqiang He High Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA

ISBN: (纸本)0818656026

Network latency, the delay caused by communication between processors and memory modules over the network in a multiprocessor system, is a major source of degraded parallel computing performance. We first give an overview of an experimental metric which uses network latency to measure and evaluate the scalability of parallel programs and architectures. We put emphasis on evaluation of latency sources and their methods in program execution. We report experimental results of evaluating the scalability of several scientific computing algorithms on the KSR-1. In comparison, we also present preliminary experiments on the CM-5 multicomputer architecture. Our comparisons indicate that the CM-5 has less network latency effects and is a more scalable architecture the the KSR-1. the analyses and experiments show that the latency metric is an important method to effectively measure overheads inherent in the program and the architecture for parallel computing scalability evaluation.< >

关键词： Scalability parallel processing Computer architecture Delay effects Laboratories Multiprocessing systems Size measurement Multiprocessor interconnection networks Helium High performance computing

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Connectivity preservation tests for parallel reduction-augmentation algorithms

Connectivity preservation tests for parallel reduction-augme...

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international conference on Pattern Recognition

作者： R.W. Hall Department of Electrical Engineering University of Pittsburgh Pittsburgh PA USA

Reduction-augmentation operators change binary images by taking certain foreground pixels to the background (reduction) and certain background pixels to the foreground (augmentation). New connectivity preservation tests have been developed for special classes of parallel 2D reduction-augmentation operators. these special classes place requirements on the operators that are typical of those which appear in existing reduction-augmentation algorithms.

关键词： Testing Pixel Labeling Smoothing methods Morphology Filling

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parallel implementation of vision algorithms on workstation clusters

Parallel implementation of vision algorithms on workstation ...

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international conference on Pattern Recognition

作者： D. Judd N.K. Ratha P.K. McKinley J. Weng A.K. Jain Department of Computer Science Michigan State University East Lansing MI USA

parallel implementations of two computer vision algorithms on distributed cluster platforms are described. the first algorithm is a square-error data clustering method whose parallel implementation is based on the well-known sequential CLUSTER program. the second algorithm is a motion parameter estimation algorithm used to determine correspondence between two images taken of the same scene. Both algorithms have been implemented and tested on cluster platforms using the PVM package. Performance measurements demonstrate that it is possible to attain good performance in terms of execution time and speedup for large-scale problems, provided that adequate memory; swap space, and I/O capacity are available at each node.

关键词： Workstations Clustering algorithms Computer vision Clustering methods Parameter estimation Layout Testing Packaging Measurement Large-scale systems

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parallel algorithms on compact binary objects

Parallel algorithms on compact binary objects

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international conference on Pattern Recognition

作者： T. Johansson E. Bengtsson Centre for Image Analysis University of Uppsala Uppsala Sweden

For SIMD computers, using virtual processors, a common strategy for mapping the processors on the image data is to apply one processor per pixel. For operations on gray level images it is a good approach, but for operations on binary images many of the available processors are idle and not used in the calculation. this paper presents some common binary operations on a new and more compact representation of the binary objects in an image, which leads to a more efficient processor utilisation and faster algorithms. the implementations are for a Connection Machine/200. the new data representation is tested on a typical application: the separation of touching objects.

关键词： parallel algorithms Shape Pixel Image analysis Electrical capacitance tomography Testing Concurrent computing Image segmentation High level languages Labeling

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Why linear arrays are better image processors

Why linear arrays are better image processors

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international conference on Pattern Recognition

作者： P.P. Jonker Pattern Recognition Section Faculty of Applied Physics Delft University of Technnology Delft Netherlands

the four main characteristic architectures for low-level image processing are the square processor array (SPA) or mesh, the linear processor array (LPA) or scanning array, the pipeline (PL) and the pyramid (PYR). In this paper a theoretical study is presented which leads from a taxonomy of low-level image processing operations and a theoretical model of a nearest neighbour connected processor to the combinations of 7 possibilities to exchange parallel for sequential solutions when designing an architecture. the implementation of two "standard" image processing routines on the theoretical processor, skeletonization of a binary image and shading correction in a greyvalue image, while making the design decisions in line with the solutions commonly found in the four characteristic architectures, showed that linear processor arrays when properly designed, seem to offer the best speed/efficiency combination even for processing images at video speed.

关键词： Clocks Image processing Pixel Taxonomy Kernel Availability Pattern recognition Physics Pipelines Logic

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