Two algorithms for LU-decomposition on a transputer based reconfigurable MIMD parallel computer with distributed memory have been analyzed in view of the interdependence of granularity and execution time. In order to ...
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An arithmetic approach, such as the Level-Finding method described in this paper for evaluating linear recursive queries in deductive database systems provides great potential for parallelprocessing. It has advantage...
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We introduce a family of massively parallel MSIMD architectures which can be configured to effectively handle a variety of different neural network models. the underlying technology is HRL's three-Dimensional Wafe...
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ISBN:
(纸本)0780308670
We introduce a family of massively parallel MSIMD architectures which can be configured to effectively handle a variety of different neural network models. the underlying technology is HRL's three-Dimensional Wafer Scale Integration (3-D WSI), which provides an ideal medium to construct powerful, compact and low-power hardware tailored for neural network processing. A second generation prototype architecture consisting of a 128 × 128 array of processors formed by stacking 16 four-inch CMOS wafers is nearing completion. the performance of this prototype is compared with enhanced architectures configured with special wafer types to accelerate neural network operations. the design of these specialized resources emphasizes the synergy between neural processing functions and the 3-D WSI architecture & packaging. Detailed microcode emulations are used to assess the impact of different algorithm/architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks. Estimated performance ranges from 2.4 billion connections per second (Giga-CPS) for the vision integration network up to 20.4 Giga-CPS for the backprop network, depending on the mapping technique and the hardware configuration.
In this paper, aimed at understanding the effects of resource utilization in the performance of multi-way joins in shared-nothing database systems, we introduce a performance modeling for the left and right-deep linea...
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