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G-SM3: High-Performance Implementation of GPU-based SM3 Hash Function 28

G-SM3: High-Performance Implementation of GPU-based SM3 Hash...

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IEEE 28th international conference on parallel and Distributed Systems (IEEE ICPADS)

作者： Dong, Jiankuo Lu, Sheng Zhang, Pinchang Zheng, Fangyu Xiao, Fu Nanjing Univ Posts & Telecommun Sch Comp Sci Nanjing Peoples R China Chinese Acad Sci Inst Informat Engn Beijing Peoples R China

ISBN: (纸本)9781665473156

Hash is one of the most important algorithms of cryptography, it is widely used in cryptographic primitives, such as digital signature, key exchange and so on. Further, hash cryptography is also the core operation of blockchain technology. With the explosive growth of the number of IoT devices and the rapid development of blockchain technology, the computing performance of hash has received widespread attention. the GPU high-performance computing platforms with a number of arithmetic cores are widely used in cryptographic optimization and acceleration. In this paper, we propose an efficient parallel accelerated framework of SM3 cryptography hash function based on GPU parallel computing devices, short for GPU-based SM3 (G-SM3). Our G-SM3 optimizes the implementation of the hash cryptographic algorithm from three aspects: parallelism, memory access and instructions. On the desktop GPU NVIDIA Titan V, the peak performance of G-SM3 reaches 23 GB/s, which is more than 7.5 times the performance of OpenSSL on a top-level server CPU (E5-2699V3) with 16 cores. On the embedded GPU which consumes less than 40 W, the SM3 throughput reaches 3.8 GB/s, which is even better than the performance of the server-level CPU. Based on the same GTX 1080, our performance is 1.12 times that of the fastest known GPU implementation, and the latency is reduced by more than 95%. Compared to other platforms, our G-SM3 has a huge advantage.

关键词： SM3 Graphic processing Unit CUDA Cryptographic Engineering

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Assignment of idle processors to spatial redistributed domains on coarse levels in multigrid reduction in time 2022

Assignment of idle processors to spatial redistributed domai...

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5th international conference on High Performance Computing in Asia-Pacific Region, HPC Asia 2022

作者： Yoda, Ryo Bolten, Matthias Nakajima, Kengo Fujii, Akihiro The University of Tokyo Japan University of Wuppertal Germany Kogakuin University Japan

ISBN: (纸本)9781450384988

parallel-in-time approaches for time-dependent PDEs have attracted a great deal of attention in the context of massively parallel environments. One such approach, multigrid reduction in time (MGRIT), extracts temporal parallelism by applying the reduction-based multigrid method for the temporal domain. To make efficient use of this parallelism, some processors need to be idle on a temporal coarse level of MGRIT. this paper proposes an optimization of the implementation that uses idle processors by assigning the spatial redistributed domain on coarse levels. It accelerates coarse-level spatial solvers and promotes early switching to parallelization-in-time by reducing its overhead. Although the spatial redistribution is contrary to the motivation of parallel-in-time approaches, it is expected to be effective when we need to balance spatial and temporal parallelism. this is because parallelization-in-time is already usually switched on when parallelization-in-space starts to saturate, so one can still benefit from additional parallelism. Numerical experiments demonstrate an improvement in runtime, at most, about 16.6% compared with pure MGRIT, which assigns best spatial and temporal parallelism at specific parallelism. © 2022 ACM.

关键词： parallel processing systems

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Single Image 3D Reconstruction Algorithm Based on parallel Double-Branch Pyramid Stacking Network 5

Single Image 3D Reconstruction Algorithm Based on Parallel D...

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2023 5th international conference on Artificial Intelligence Technologies and Applications, ICAITA 2023

作者： Ku, Yintao Zhang, Yumei Yang, Honghong Zhao, Yanqing Li, Jinshan Zhou, Yulin Wu, Xiaojun Key Laboratory of Modern Teaching Technology Ministry of Education Shaanxi Normal University Xi'an China School of Computer Science Shaanxi Normal University Xi'an China Key Laboratory of Intelligent Computing and Service Technology for Folk Song Ministry of Culture and Tourism Xi'an China

Limited visual information contained in single images and complex motion models of objects may lead to severe fragmentation and confusion of model backbone in the 3D reconstruction of objects. In order to fully extract feature information in a single image and reduce noise interference caused by environmental factors in 3D reconstruction, a parallel Dual-Branch Pyramid Stacking Network (PDB-PSN) model is proposed. A parallel dual-branch network model is used to construct an encoder-decoder framework based on cascaded feature extraction, encode/decode high and low-resolution features in a single image, and then convert from 2D to 3D through implicit functions to achieve the 3D reconstruction of target objects in a single image. A cascaded feature extraction network is used as a low-resolution feature extraction network to extract global features of objects. In the high-resolution feature extraction branch, three concatenated hourglass networks and dilated convolutions are used in the hourglass network to increase the receptive field and obtain more global information in order to maintain the integrity of the reconstructed object limbs. A threshold processing module is set to remove irrelevant information and ensure the integrity of global information, and meanwhile, to reduce the interference of irrelevant noise information. Simulation experiments on a self-built terracotta dataset show that the PDB-PSN model can completely reconstruct the 3D model in a single image and effectively eliminate model fragmentation in the reconstruction results. © Published under licence by IOP Publishing Ltd.

关键词： Feature extraction

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A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 Counter in a Wallace Tree Structure

A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 C...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Saleem Syed Abdul Khader Khaderabad Sahithi Ankirapalli Swathi Lingamgunta Sasi Priyanka thammisetty Jaffar Ali Syed Dept. of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences Kadapa India

ISBN: (数字)9798331544607

ISBN: (纸本)9798331544614

It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. this longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallel processing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. this will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. this method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. this helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.

关键词： Micromechanical devices Power demand Logic gates parallel processing Market research Delays Table lookup Informatics Adders Optimization

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A Comparative Analysis on Sarcasm Detection

A Comparative Analysis on Sarcasm Detection

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Cybernetics, Cognition and Machine Learning Applications (ICCCMLA), IEEE international conference on

作者： Arghya Bhattacharjee Ajey Kumar Dhanya Promod Symbiosis Centre for Information Technology Symbiosis International (Deemed University) Pune India

Sarcasm detection is a difficult challenge in Natural Language processing as it needs to understand the speaker's intention, which can be opposite to the actual meaning of the words used Recent advancements in sarcasm detection have been made using machine learning techniques such as various text embedding techniques with context-aware pre-trained deep learning architectures. this research work is a comparative analysis of various machine learning models on two different publicly available datasets- iSarcasm and News Headlines dataset. Upon using the same parameters, the Ensemble machine learning models have better performed on varied, smaller yet imbalanced iSarcasm dataset, whereas complex deep learning models have given better results on structured, larger and balanced News Headlines dataset.

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Designing a 3D parallel Memory-Aware Lattice Boltzmann Algorithm on Manycore Systems 27th

Designing a 3D Parallel Memory-Aware Lattice Boltzmann Algor...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Fu, Yuankun Song, Fengguang Purdue Univ Indianapolis IN USA Indiana Univ Purdue Univ Indianapolis IN 46202 USA

ISBN: (纸本)9783030856656;9783030856649

Lattice Boltzmann method (LBM) is a promising approach to solving Computational Fluid Dynamics (CFD) problems, however, its nature of memory-boundness limits nearly all LBM algorithms' performance on modern computer architectures. this paper introduces novel sequential and parallel 3D memory-aware LBM algorithms to optimize its memory access performance. the introduced new algorithms combine the features of single-copy distribution, single sweep, swap algorithm, prism traversal, and merging two temporal time steps. We also design a parallel methodology to guarantee thread safety and reduce synchronizations in the parallel LBM algorithm. At last, we evaluate their performances on three high-end manycore systems and demonstrate that our new 3D memory-aware LBM algorithms outperform the state-of-the-art Palabos software (which realizes the Fuse Swap Prism LBM solver) by up to 89%.

关键词： Lattice Boltzmann method Memory-aware algorithms parallel numerical methods Manycore systems

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Application of Massive parallel Computation Based Q-Learning in System Control 5

Application of Massive Parallel Computation Based Q-Learning...

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5th international conference on Pattern Recognition and Artificial Intelligence, PRAI 2022

作者： Huang, Demei Zhu, Haoyuan Lin, Xianqi Wang, Li Guangzhou Institute of Science and Technology Intelligent Manufacturing and Electrical Engineering College GuangZhou China Guangdong Sanchen Intelligent Technology Co . Ltd. Engineering Department GuangZhou China

ISBN: (数字)9781665499163

ISBN: (纸本)9781665499163

the Q-Learning algorithm is a reinforcement learning algorithm based on continuous decision-making and satisfying the Markov decision process property (MDP), and its agent operating environment also has dynamic uncertainties. Due to the existence of such a framework, the Q-Learning algorithm can be widely used in complex real-world problems, such as intelligent robots, industrial control, games, etc. However, Q-Learning is also a very slow method, which requires a long training time and computing resources to obtain a practical convergence strategy, such as obtaining a path between any two points on a map of size 21*10. the converged policy takes about 1200 seconds. Importantly, this time increases exponentially with the size of the map. this in turn limits its application in practical problems. Super computer or cloud-based computation could be a solution to this problem. However, both are too expensive to small and medium scaled entities. Other alternatives could be multithreading and GPU. In contrast to the traditional single thread Q-learning algorithm which utilize only part of hardware capacity, they can fully utilize hardware. In addition, they are far more affordable for most entities. In addition, there are enough mature support materials for this hardware. this paper attempts to improve this problem by proposing a model that uses shared Q-tables, multithreading, and GPU based massively parallel computing. this solution can give full play to the performance of hardware devices and achieve the goal of increasing the algorithm convergence speed by dozens of times without increasing hardware costs. It effectively lowers the threshold for using reinforcement learning technology. © 2022 IEEE.

关键词： Graphics processing unit

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Research on the Application of Natural Language processing Technology in Medicine Patent Retrieval

Research on the Application of Natural Language Processing T...

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Information Science, parallel and Distributed Systems (ISPDS), international conference on

作者： Lan Tu Shuojun Lv Hui Shi Department of Information Engineering Shanwei Polytechnic Shanwei China Research Institute of Cloud Computing and Data Center Project Design Shanwei Innovation Industrial Design and Research Institute Shanwei China

ISBN: (数字)9798350352719

ISBN: (纸本)9798350352726

In view of the high professionalism and complexity of medicine patent text, traditional patent retrieval mainly relies on manual operation and simple text processing methods, this paper aims to use Natural Language processing (NLP) technology to efficiently obtain valuable information in medicine patent retrieval. To transform unstructured text into meaningful information. through in-depth research on the characteristics and structure of medicine patent text, a new structured feature extraction algorithm of patent text is proposed, and a patent retrieval system based on NLP is developed, which can carry out instant structured processing, and can automatically identify and translate text into corresponding patented medicines, and nearly 300 medicine patent abstracts are tested by experiment. the system performance is good. the system achieves the expected effect.

关键词： Training Patents Adaptation models Transfer learning Transforms Search problems Natural language processing

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parallel Computation of Hadamard Product for Dynamic Dataset on Google Colab 5th

Parallel Computation of Hadamard Product for Dynamic Datas...

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5th international conference on Information and Communication Technology for Intelligent Systems, ICTIS 2021

作者： Shariar, Sarjil Hasan, K. M. Azharul Department of Computer Science and Engineering Khulna University of Engineering & Technology Khulna Bangladesh

ISBN: (纸本)9789811641763

Hadamard product, the element-wise product of tensors, is an important tool for many real-life applications such as machine LSTM, multimodal learning, object recognition, and segmentation. In this paper, we propose a faster processing of hadamard product by the parallel computation on graphics processing unit (GPU) for dynamic data. Most of the computations for real-life data are multidimensional and dynamic which expand during run time. In this scheme, we use dynamic memory allocation that allows further expansion of the dimension size and high memory utilization based on the notion of extendable array. Since high dimensionality is difficult to handle, we use a dimension conversion technique where the n-dimensional array structure is transformed into a 2-dimensional structure. Furthermore, to handle the future data, we apply the converted extendable array structure to get Scalable Hadamard Product (SHDP) for dynamic dataset. then, we implement a parallel algorithm for the parallel processing of the SHDP that partitions and distributes the element-wise product during runtime. We utilize the maximum available GPU threads for the faster performance of the hadamard product. We found good speed-up for the proposed partitioning while applying to "Google Colab". © 2022, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Graphics processing unit

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Lightweight Bimodal Rail Surface Defect Detection Method: parallel-YOLOv4-Tiny 5

Lightweight Bimodal Rail Surface Defect Detection Method: Pa...

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5th international conference on Video and Image processing (ICVIP)

作者： Zheng, Jiajun Han, Qiang Wang, Le Wang, Shengchun Zhang, Zhiyong Wang, Luping Wang, Liang Sun Yat Sen Univ Sch Elect & Commun Engn Guangzhou Peoples R China China Acad Railway Sci Corp Ltd Beijing Peoples R China

ISBN: (纸本)9781450385893

Rail defect has been harmful to the safety of railway operation for a long time. At present, there is an urgent need for a fast and high-precision rail surface defect detection method which can be applied to comprehensive inspection vehicles. In this paper, we propose a lightweight Bimodal Rail Surface Defect Detection Method, called parallel-YOLOv4-Tiny, for bimodal rail surface defect images. We design a parallel feature processing strategy for bimodal image feature extraction in parallel-YOLOv4-Tiny. A series of experiments show that parallel-YOLOv4-Tiny with CIOU loss function can achieve a mAP of 92.07 at 88 FPS on a single GPU. parallel-YOLOv4-Tiny has a much better performance than other original YOLOv4-Tiny methods, which shows the validity and advancement of parallel-YOLOv4-Tiny. parallel-YOLOv4-Tiny can meet the practical application requirements of high-speed railways and improve the efficiency of daily railway patrol inspection.

关键词： lightweight network bimodal rail surface defect detection parallel-YOLOv4-Tiny

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