Improvements in disk speed have not kept up with improvements in processor and memory speed. Conventional storage techniques, in the face of multimedia data, are inefficient and/or inadequate. An efficient multimedia ...
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We propose a parallel algorithm which reduces the problem of computing Hamiltonian cycles in tournaments to the problem of computing Hamiltonian paths. the running time of our algorithm is O(log n) using O(n2/log n) p...
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In this paper, we present algorithms for solving several basic geometric problems of size n in a network of p processors each with O(n/p) local memory. Our algorithms achieve the best possible (up to a constant factor...
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In this paper, we present algorithms for solving several basic geometric problems of size n in a network of p processors each with O(n/p) local memory. Our algorithms achieve the best possible (up to a constant factor) time bound in hypercubic parallelarchitectures such as hypercube, shuffle exchange and cube connected cycles, provided that n /spl les/ p/sup 1/+/spl epsi/ for some positive constant /spl epsi/. Our algorithms use only sorting and parallel prefixes that involve interprocessor communications, and can be easily implemented in commercially available parallel computers. Experimentation on nCUBE parallel computers show that our algorithms run efficiently.< >
Data-parallel ML is proposed for compilation to a distributed version (DPCAM) of Cousineau, Curien and Mauny’s Categorical Abstract Machine. the DPCAM is a static network of CAMs which dynamically restrict the MIMD e...
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the authors present a testability analysis and testing approach for local and global interconnection topologies for single and multiple faulty cells. Fault location can be obtained for single faulty cells, while for m...
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ISBN:
(纸本)0780308670
the authors present a testability analysis and testing approach for local and global interconnection topologies for single and multiple faulty cells. Fault location can be obtained for single faulty cells, while for multiple cells fault masking can be identified, and fault location can be obtained iteratively. the approach is based on the analysis of controllability and observability of the architecture given the cell function and the interconnection topology. the input output relationship of the generic cell is the cell function. A fault model is derived for multistage interconnection networks. the testing method can be applied to any architecture independently of its topology, and of the number of input and output lines of the generic cell contained in it.
Cost-effective multiprocessor designs may be obtained by combining processors of different speeds (heterogeneous architecture) in the same architecture. this way, the serial and critical portions of the application ma...
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this paper addresses the problem of constructing a work load balanced parallel multi-way merge. While a balanced multi-way merge provides an ideal component for multiprocessor sorting algorithms, the general problem c...
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We investigate synchronization activities in application executing on distributed-memory MIMD architectures. three applications are used to quantify the performance impact of synchronization as the number of processor...
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We investigate synchronization activities in application executing on distributed-memory MIMD architectures. three applications are used to quantify the performance impact of synchronization as the number of processors is increased. We also investigate the performance improvement possible when synchronization is supported in hardware. the results show that significant performance improvement can be achieved. the hardware support should include barrier synchronization, operate-and-broadcast, and operations over subsets of processors.< >
the GRIP architecture allows efficient execution of functional programs on a multi-processor built from standard hardware components. State-of-the-art compilation techniques are combined with sophisticated runtime res...
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this paper deals withthe problem of task allocation, subjected to precedence constraints, on multiprocessor architectures with interprocessor communication delays. Two kinds of scheduling are distinguished: the deter...
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