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Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA

Sparse Matrix-Vector Multiplication Based on Network-on-Chip...

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international conference on Computer and Information Technology (CIT)

作者： Chi-Chia Sun Jürgen Götze Hong-Yuan Jheng Shanq-Jang Ruan Information Processing Lab Dortmund University of Technology Dortmund Germany Low-Power System Lab National Taiwan University of Science and Technology Taipei Taiwan

A new method for performing Sparse Matrix-Vector Multiplication (SMVM) by using Network-on-Chip (NoC) architecture is described. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections or shared-buses. therefore, regular local data transfer is the major concern of many parallel implementations. However, when dealing with the parallel implementation of SMVM, which is the main step of all iterative algorithms for solving system of linear equations, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using a NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have implemented the proposed SMVM calculator based on NoC architecture with the size of 4 × 4 and 5 × 5 in IEEE 754 single float point precision using FPGA.

关键词： Sparse matrices Field programmable gate arrays Computer architecture Switches System-on-a-chip Routing Equations

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Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Archite...

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Proceedings of the 13th international conference on Distributed Smart Cameras

作者： Walther Carballo-Hernández François Berry Maxime Pelcat Miguel Arias-Estrada Department of Images Perception Systems and Robotics Institut Pascal Aubière France Department of Images Institut National des Sciences Appliquées (INSA) des Rennes IETR UMR CNRS Rennes France Department of Computer Science Instituto Nacional de Astrofísica (Óptica y Electrónica (INAOE) Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia® Jetson TX2 for the CPU-GPU side and an Intel Altera® Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Internet of things Field Programmable Gate Array (FPGA) Graphic processing Unit (GPU) Deep Learning (DL) Edge Computing processing Elements (PE) Artificial Neural Networks (ANN) Single Instruction Multiple Data Convolutional Neural Networks (CNN) Models of Computation and Architecture Pipelining Heterogeneous Computing parallel Programming

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Intrusion Detection System Using Machine Learning Techniques for Increasing Accuracy and Distributed & parallel Approach for Increasing Efficiency

Intrusion Detection System Using Machine Learning Techniques...

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international conference on Computing Communication Control and Automation (ICCUBEA)

作者： Abhijit D. Jadhav Vidyullatha Pellakuri Department of Computer Science & Engineering Koneru Lakshmaiah Education Foundation Vaddeswaram A.P. India

ISBN: (数字)9781728140421

ISBN: (纸本)9781728140438

In the current era of wide use of internet by the users across the globe, the data generated and its security both are the important issues. Hence, in any network to prevent the malicious activities from the intrusions, the early and correct detection of intruders is important. For that we are using Intrusion Detection systems (IDS), developed with many effective algorithms which are helping us to get rid of these attacks. But, sometimes these systems do respond with the detection of intruders who are in real, not the intruders, but the normal users. this makes these users difficult to continue with the normal communication and can be prevented from accessing the important services over the World Wide Web. Similarly, not tolerable at all, when it's false negative i.e. intruder is allowed to enter into network traffic being a normal user, as it may cost to an organization to the extent of being demolished their future. though the percentage of these false positives and false negatives is less, it is creating issues in many important services. For that we can have a machine learning techniques which can effectively detect intrusions in the system without creating obstacles of false positives and false negatives, also we are proposing it for the online streamed data. Also, this IDS implementation using machine learning techniques is proposed with Distributed & parallel approach for simultaneous processing of network traffic data by these different machine learning techniques. this approach enables us to implement this IDS design for Online streamed data for faster detection i.e. increasing efficiency of IDS.

关键词： accuracy false negatives false positives intrusion detection machine learning techniques

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Peak Power Management for scheduling real-time tasks on heterogeneous many-core systems

Peak Power Management for scheduling real-time tasks on hete...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Waqaas Munawar Heba Khdr Santiago Pagani Muhammad Shafique Jian-Jia Chen Jörg Henkel Karlsruhe Institute of Technology (KIT) Germany Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE

the number and diversity of cores in on-chip systems is increasing rapidly. However, due to the thermal Design Power (TDP) constraint, it is not possible to continuously operate all cores at the same time. Exceeding the TDP constraint may activate the Dynamic thermal Management (DTM) to ensure thermal stability. Such hardware based closed-loop safeguards pose a big challenge in using many-core chips for real-time tasks. Managing the worst-case peak power usage of a chip can help toward resolving this issue. We present a scheme to minimize the peak power usage for frame-based and periodic real-time tasks on many-core processors by scheduling the sleep cycles for each active core and introduce the concept of a sufficient test for peak power consumption for task feasibility. We consider both inter-task and inter-core diversity in terms of power usage and present computationally efficient algorithms for peak power minimization for these cases, i.e., a special case of “homogeneous tasks on homogeneous cores” to the general case of “heterogeneous tasks on heterogeneous cores”. We evaluate our solution through extensive simulations using the 48-core SCC platform and gem5 architecture simulator. Our simulation results show the efficacy of our scheme.

关键词： Power demand Schedules Real-time systems Multicore processing Minimization Partitioning algorithms thermal management

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Research of Control Methods of a Spherical parallel Mechanism Using Intelligent Data processing

Research of Control Methods of a Spherical Parallel Mechanis...

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international conference on Modern Electrical and Energy Systems (MEES)

作者： A. Derkachenko O. Polyvoda Yu. Lebedenko K. Kalinina Automation Robotics and Mechatronics Department Kherson National Technical University Kherson Ukraine Information and Computer Technologies Department Kyiv National University of Technologies and Design Kyiv Ukraine

the work is devoted to the research and development of a software and hardware platform based on control methods of a spherical parallel mechanism (SPM) with tracking of changes in the position of a human head with the help of a camera and a computer using intelligent data *** article explores the relevance and advantages of SPMs, emphasizing their high precision, enhanced mobility, reliability, and lightweight design. the paper deals with an important aspect of controlling SPMs, which directly influences their performance. the control methods for SPMs vary based on the specific tasks and operational requirements, such as actuator-based control, sensor-based control, closed-loop control, and adaptive control are *** research additionally investigates the problems of forming tasks for SPMs and the need for improved methods, especially for applications involving human-robot interaction, dangerous works, and camera positioning tasks. To resolve these problems, the study proposed a software-hardware platform that remotely controls SPMs by tracking changes in the position of the human head using a camera and a computer. By employing OpenCV and Dilb libraries for face recognition and control point tracking, the proposed platform enables intuitive and clear control of the *** article presents the mathematical operations involved in calculating the rotation angles of the SPM based on the tracked human head movements. the obtained rotation angles serve as inputs for the servomotors, allowing precise control over the mechanism's *** results of the study demonstrate the effectiveness of the proposed software-hardware platform in controlling the SPM based on human head movements. the platform's ability to accurately track and convert head movements into servo rotation values enables remote and intuitive control of the SPM, making it a promising direction for future research in the field of robotics and automation.

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Analysis and Implementation of a parallel Computing Cluster for Solving Computational Problems in Data Analytics

Analysis and Implementation of a Parallel Computing Cluster ...

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IEEE international conference on Computing, Communication and Security (ICCCS)

作者： Chavala Mutyala Rao K. Shyamala University College of Engineering Osmania University Hyderabad

ISBN: (数字)9781728191805

ISBN: (纸本)9781728191812

As computers get updated by a couple of generations, they get disposed of as useless but when a large number of such computers are put together and they share each other's computational power, they can get really powerfulcluster defines as a parallel computing system which is inter connected with a group of independent computers working togeather as a single coherent system. Clusters uses message passing interface for communication, and code snippets have to be explicitly programmed to run on underlying hardware. More computing nodes to be added to the cluster based on the need. While designing parallel cluster in many cases we opt for open source technologies and Linux system components which reduce software costs. parallel Cluster is a way of connecting similar computers together and can get a task done by sharing the task load. the task is shared in coordination of the master and slave nodes in a cluster. parallel computing clusters allows group of computers with different hardware configurations, to work together to provide solutions to different computational problems. the resources like memory, storage and CPU cores in a cluster computing environment are integrated into one system. this paper is to set up a cluster environment for academic purposes and provide a huge computation power to run a program in parallel mode this will reduce the time taken to execute a program. A parallel code is always better then sequential code in terms of time taken to run.

关键词： Rocks Servers Task analysis parallel processing Linux Hardware Performance evaluation

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Compiling code accelerators for FPGAs

Compiling code accelerators for FPGAs

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Walid A. Najjar Computer Science & Engineering University of California Riverside Riverside CA USA

this tutorial addresses the challenges and opportunities presented by compiled FPGA-based code accelerators. In recent years we have witnessed a fast growth of both size and speed of FPGAs. these had been initially designed and marketed as convenient devices for “glue logic.” Later, they became used as fast prototyping platforms. As their size and speed grew, they have been used for the short time to market they can afford. Lately, their size and speed have made them attractive as code accelerator. While the clock speed achievable on a typical FPGA design is about an order of magnitude lower than that on a typical CPU, their advantage comes from two sources: (1) Large degree of instruction and loop level parallelism. parallel loops can typically be unrolled by factors ranging in the 100s. (2) Increased efficiency of hardware execution. the streaming of the data through a dedicated circuit eliminates a large number of support operations such as data fetch, address calculations, index management, loop control, etc. the combined higher efficiency and parallelism of hardware execution on FPGAs has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processor on frequently executed code segments. However, the main obstacle to wider acceptance of this technology is programmability. FPGAs are typically programmed using Hardware Description Languages (HDLs), which poses two problems: Traditional application developers are typically not HDL designers, and HDLs are not well suited for algorithm implementation. Furthermore, the FPGA is an amorphous mass of logic on which the compiler must create a data-path and schedule the computation. Such a task requires the harnessing of technologies developed for parallelizing compilers as well as those developed for high-level synthesis. the main challenge that faces HLL to HDL translation is the paradigm shift from the stored program model to a value-based, data-driven execution - that is, from temporal

关键词： Field programmable gate arrays Hardware design languages parallel processing Hardware Tutorials Computer architecture Clocks

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G-SM3: High-Performance Implementation of GPU-based SM3 Hash Function

G-SM3: High-Performance Implementation of GPU-based SM3 Hash...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Jiankuo Dong Sheng Lu Pinchang Zhang Fangyu Zheng Fu Xiao School of Computer Science Nanjing University of Posts and Telecommunications Nanjing China Chinese Academy of Sciences Institute of Information Engineering Beijing China

Hash is one of the most important algorithms of cryptography, it is widely used in cryptographic primitives, such as digital signature, key exchange and so on. Further, hash cryptography is also the core operation of blockchain technology. With the explosive growth of the number of IoT devices and the rapid development of blockchain technology, the computing performance of hash has received widespread attention. the GPU high-performance computing platforms with a number of arithmetic cores are widely used in cryptographic optimization and acceleration. In this paper, we propose an efficient parallel accelerated framework of SM3 cryptography hash function based on GPU parallel computing devices, short for GPU-based SM3 (G-SM3). Our G-SM3 optimizes the implementation of the hash cryptographic algorithm from three aspects: parallelism, memory access and instructions. On the desktop GPU NVIDIA Titan V, the peak performance of G-SM3 reaches 23 GB/s, which is more than 7.5 times the performance of OpenSSL on a top-level server CPU (E5-2699V3) with 16 cores. On the embedded GPU which consumes less than 40 W, the SM3 throughput reaches 3.8 GB/s, which is even better than the performance of the serverlevel CPU. Based on the same GTX 1080, our performance is 1.12 times that of the fastest known GPU implementation, and the latency is reduced by more than 95%. Compared to other platforms, our G-SM3 has a huge advantage.

关键词： Performance evaluation Hash functions Instruction sets Graphics processing units parallel processing throughput Blockchains

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High-Performance Computation of LGCA Fluid Dynamics on an FPGA-Based Platform

High-Performance Computation of LGCA Fluid Dynamics on an FP...

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international conference on Computers, Communications, and Systems (ICCCS)

作者： Changdao Du Iman Firmansyah Yoshiki Yamaguchi University of Tsukuba Tsukuba Japan

ISBN: (数字)9781728161365

ISBN: (纸本)9781728161372

Lattice Gas Cellular Automata (LGCA) simulations are typical High-Performance Computing (HPC) applications commonly used to simulate fluid flows. Due to the computational locality and discretization of LGCA, these simulations can achieve high performance by using parallel computing devices like GPUs or multi-core CPUs. Nevertheless, many studies also have shown that state-of-the-art Field Programmable Gate Arrays (FPGAs) have enormous parallel computing potential and power-efficient for high-performance computations. In this paper, we present an FPGA-based fluid simulation architecture design for the LGCA method. Our design exploits both temporal and spatial parallelism inside the LGCA algorithm to scale up the performance on FPGA. We also propose an application-specific cache structure to overcome the memory bandwidth bottleneck. Furthermore, our development process is based on the High-Level Synthesis (HLS) approach that increases productivity. Experimental results on a Xilinx Vcu 1525 FPGA show that our design is able to achieve 17130.2 Million Lattice Updates Per Second (MLUPS).

关键词： Lattices Field programmable gate arrays parallel processing Computer architecture Computational modeling Mathematical model Bandwidth

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Advanced Stochastic Approaches for Applied Computing in Environmental Modeling 14th

Advanced Stochastic Approaches for Applied Computing in En...

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14th international conference on parallel processing and Applied Mathematics, PPAM 2022

作者： Todorov, Venelin Dimov, Ivan Ganzha, Maria Paprzycki, Marcin Department of Information Modeling Institute of Mathematics and Informatics Bulgarian Academy of Sciences Acad. Georgi Bonchev Street Block 8 Sofia1113 Bulgaria Department of Parallel Algorithms Institute of Information and Communication Technologies Bulgarian Academy of Sciences Acad. G. Bonchev Street Block 25 A Sofia1113 Bulgaria Polish Academy of Sciences Warszawa Poland

ISBN: (纸本)9783031304415

Mathematical models are used to study and predict the behavior of a variety of complex systems - engineering, physical, economic, social, environmental. Sensitivity studies are nowadays applied to some of the most complicated mathematical models from various intensively developing areas of applications. Sensitivity analysis is a modern promising technique for studying large-scale systems such as ecological systems. the uncertainty in the model input in our case, as in many others, can be due to various reasons: inaccurate measurements or calculation, approximation, data compression, etc. Two kinds of sensitivity analysis have been discussed in the literature: local and global. In the current paper the subject of our study is the global sensitivity analysis performed via the Sobol’ variance-based approach, applied to a specific large-scale air pollution model. the mathematical treatment of the problem of providing global sensitivity analysis consists in evaluating total sensitivity indices which leads to computing multidimensional integrals. We propose a new specific stochastic approach which significantly improves the results by the standard stochastic approaches. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Monte Carlo methods

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