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Proceedings of the 5th ACM international conference on Distributed event-based system

作者： Visalakshmi Suresh Paul Ezhilchelvan Paul Watson Cuong Pham Dan Jackson Patrick Olivier Newcastle University Newcastle Upon Tyne United Kingdom Newcastle University Newcastle upon tyne United Kingdom

ISBN: (纸本)9781450304238

Stream-processing systems inevitably face unpredictable variations in incoming event loads. One way of handling this without affecting end-to-end performance metrics, will be to dynamically distribute event-processing on multiple computers and thus avail compute power for optimal performance. More precisely, data streams are processed in part or in parallel on multiple computers connected by a high bandwidth network. the number of computers being used is to be varied dynamically to cope with input load fluctuations. this paper uses data from ambient kitchen to make a preliminary assessment of performance advantages by distribution of real-time data stream processing. the motivation is to leverage cloud computing for optimal realtime event processing.

关键词： real time and embedded systems distributed applications performance attributes

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Time series mining at petascale performance 35th

Time series mining at petascale performance

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35th international conference on High Performance Computing, ISC High Performance 2020

作者： Raoofy, Amir Karlstetter, Roman Yang, Dai Trinitis, Carsten Schulz, Martin Computer Architecture and Parallel Systems Technical University of Munich Garching Germany IfTA GmbH Puchheim Germany NVIDIA Munich Germany

ISBN: (纸本)9783030507428

the mining of time series data plays an important role in modern information retrieval and analysis systems. In particular, the identification of similarities within and across time series has garnered significant attention and effort over the last few years. For this task, the class of matrix profile algorithms, which create a generic structure that encodes correlations among records and dimensions—the matrix profile—is a promising approach, as it allows simplified post-processing and analysis steps by examining the resulting matrix profile structure. However, it is expensive to create a matrix profile: it requires significant computational power to evaluate the distance among all subsequence pairs in a time series, especially for very long and multi-dimensional time series with a large dimensionality. Existing approaches are limited in their scalability, as they do not target High Performance Computing systems, and—for most realistic problems—are suited only for datasets with a small dimensionality. In this paper, we introduce a novel MPI-based approach for the calculation of a matrix profile for multi-dimensional time series that pushes these limits. We evaluate the efficiency of our approach using an analytical performance model combined with experimental data. Finally, we demonstrate our solution on a 128-dimensional time series dataset of 1 million records, solving 274 trillion sorts at a sustained 1.3 Petaflop/s performance on the SuperMUC-NG system. © Springer Nature Switzerland AG 2020.

关键词： Time series

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A Comparative Analysis of 8-Bit parallel Prefix Adder architectures

A Comparative Analysis of 8-Bit Parallel Prefix Adder Archit...

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Smart Electronics and Communication (ICOSEC), international conference on

作者： M. Bharathi V Madhurima G. Sandhyakumari M. Poornima Saleha Tabassum Electronics and Communication Engineering Mohan Babu University Tirupati Andhra Pradesh India Electronics and Communication Engineering S V College of Engineering Tirupati AndraPradesh India Electronics and Communication Engineering Siddartha Institute of Science and Technology Puttur AndraPradesh India Electrical and Electronics Engineering KSRMCE Kadapa AndraPradesh India

ISBN: (数字)9798331504403

ISBN: (纸本)9798331504410

Digital adders are crucial parts of contemporary computer systems that influence the efficiency of specific arithmetic processes. parallel prefix adders, like Sparse Kogge, Hancarlson and Brent Kung enhance performance by calculating results leading to faster and more efficient arithmetic operations compared to traditional adders that process data sequentially. this paper thoroughly compares four 8 bit designs; Sparse Kogge, Han Carlson, Brent Kung and Binary Coded Decimal (BCD) adder. Evaluation criteria include propagation latency (ns) power consumption (W) and area utilization (LUTS). When comparing the Brent Kung adder with the BCD adder there is a 18.33% increase in propagation delay but a significant 83.87% decrease in power consumption and a fifty percent reduction in area usage. the primary focus of the Hancarlson adder is power efficiency leading to an ${8 7. 1 0 \%}$ drop in power usage but a substantial 93.49% increase in propagation latency. the Sparse Kogge adder strikes a balance with a 58.06% decrease in power consumption and a moderate 18.75% reduction in area utilization while maintaining a propagation delay, as the BCD adder. these results illustrate trade-offs between various adder architectures in terms of power, latency, and area utilization. these designs are designed and simulated using Xilinx Vivado 2022.2 software.

关键词： Energy consumption Power demand Costs Computer architecture Software Table lookup Resource management Adders Propagation delay Arithmetic

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BPPV-Chain: A Sharding Blockchain System with Output Shard Batch processing and parallel Transaction Verification 23

BPPV-Chain: A Sharding Blockchain System with Output Shard B...

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Proceedings of the 2023 5th international conference on Blockchain Technology

作者： Jinfeng Ding Qihua Hu Changkai Lin Minglin Shi Hongju Cheng Fuzhou University China

ISBN: (纸本)9798400708930

the current sharding schemes show some shortcomings, such as poor performance while handling cross-shard transactions, and the transactions are verified in an inefficient way. A sharding blockChain system with output shard Batch processing and parallel transaction Verification(BPPV-Chain) is proposed in this study. the core idea of the proposed scheme is elucidated as follows. the output shard is capable of verifying and processing the input availability certificates generated by the input shard in a batch manner, and it can generate the transaction availability certificates of different input shards when coping with the cross-shard transactions. the input shard unlocks or spends UTXO following the transaction avaliability certificates to for the cross-shard collaboration. On that basis, the communication complexity of cross-shard transactions can be reduced. Moreover, a parallel transaction verification scheme is present to increase the efficiency of transaction verification. In this scheme, UTXO is verified in a serial manner to prevent double spending and the signatures and values of multiple transactions are checked in a parallel manner. As indicated by the experimental results, BPPV-Chain outperforms existing sharding blockchain systems especially under the percentage of cross-shard transactions of not more than 80%. Furthermore, BPPV-Chain also ensures linear growth of throughput with the number of shards increasing, such that the scalability of BPPV-Chain can be confirmed.

关键词： Blockchain Cross-shard transaction Output shard batch processing parallel verification Sharding

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High-speed parallel DSP architecture dedicated to digital modem applications

Proceedings of the IEEE International Conference on Electron...

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Proceedings of the IEEE international conference on Electronics, Circuits, and Systems 1998年 1卷 477-480页

作者： Philip, S. Monteiro, F. Dandache, A. Lepley, B. Univ of Metz Metz France

this paper presents the architecture of a high-speed Digital Signal Processor (DSP) designed for high rate digital modem applications. this work stands as a part of an EURICO European project, whose target is the design of a TV cable modem. First, some aspects of the TV cable digital modem application are presented. then, the paper describes the DSP architecture, based on a VLIW core processor and on Auxiliary Dedicated Modules (ADM). the architectural choices and the main advantages are discussed. Last, the general structure of the ADMs is discussed through an example: the implementation of a Cyclic Redondancy Checking (CRC) dedicated ADM.

关键词： Digital signal processing

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Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

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Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

the desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. these systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. this new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

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An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core architectures

An Adaptive Block Pinning Cache for Reducing Network Traffic...

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international conference on Computational Intelligence and Communication Networks (CICN)

作者： Nitin Chaturvedi S. Gurunarayanan Electrical Electronics Engineering Department Birla Institute of Technology and Science Pilani India

With advent of new technologies there is exponential increase in multi-core processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this issue. A NUCA partitions the complete cache memory into smaller multiple banks and allows banks near the processor cores to have lower access latencies than those further away, thus reducing the effects of the cache's internal wire delays. Traditionally, NUCA organizations have been classified as static (S-NUCA) and dynamic (D- NUCA). While in S-NUCA a data block is mapped to a unique bank in the NUCA cache, D-NUCA allows a data block to be mapped in multiple banks. In D-NUCA designs a data blocks can migrate towards the processor core that access them most frequently. this migration of data blocks will increase network traffic. the short life time of data blocks and low spatial locality in many applications results in eviction of block with few unused words. this effectively increases miss rate, and waste on chip network bandwidth. Unused word transfers also wastes a large fraction of on chip energy *** this paper, we present an efficient and implementable cache design that eliminate unnecessary coherence traffic and match data movements to an applications spatial locality. It also presents one way to scale on-chip coherence with less costeffective techniques such as shared caches augmented to track cached copies, explicit eviction notification and hierarchal design. Based on our scalability analysis of this cache design we predict that this design consistently reduce miss rate and improve the fraction of data transmitted that is actually utilized by the application.

关键词： Coherence Arrays Protocols Bandwidth Multicore processing Hardware

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An Automatic parallel-Stage Decoupled Software Pipelining parallelization Algorithm Based on OpenMP

An Automatic Parallel-Stage Decoupled Software Pipelining Pa...

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IEEE international conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Xiaoxian Liu Rongcai Zhao Lin Han Peng Liu State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China

ISBN: (纸本)9781479914449

While multicore processors increase throughput for multi-programmed and multithreaded codes, many important applications are single threaded and thus do not benefit. Automatic parallelization techniques play an important role in migrating singe threaded applications to multicore platforms. Unfortunately, the prevalence of control flow, recursive data structures, and general pointer accesses in ordinary programs renders the traditional automatic parallelization techniques unsuitable. parallel-Stage Decoupled Software Pipelining (PS-DSWP) is proposed to exploit fine-grained pipeline parallelism lurking in ordinary programs with the existence of all kinds of dependences, including arbitrary control dependences, at the instruction level. But it requires knowledge of architectural properties and hardware support of a communication channel and two special instructions. We propose an improved PS-DSWP algorithm based on OpenMP in this paper. It is implemented without relying on CPU architectures by using a high level intermediate representation. Moreover, the Program Dependence Graph (PDG) used in the algorithm is built based on the basic blocks, which exploits coarser-grained parallelism than the original PS-DSWP transformation with PDG based on instructions. OpenMP is employed in our algorithm to assign task and implement synchronization among threads while avoiding dependence on hardware support. We evaluate the loops with complex memory patterns and control flow, which cannot be dealt with by traditional techniques, on multicore platform. As a result, they can be parallelized and gain significant performance improvement with our algorithm. We obtain a maximum speedup as high as 2.07x and on average 1.39x with 5 threads.

关键词： Instruction sets Synchronization Pipeline processing Multicore processing Merging

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SPD-RAID4: Splitting Parity Disk for RAID4 Structured parallel SSD Arrays

SPD-RAID4: Splitting Parity Disk for RAID4 Structured Parall...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Wen Pan Feng Liu Tao Xie Yanyan Gao Yiming Ouyang Tian Chen Computer & Information School Hefei University of Technology Hefei Anhui China Computer Science Department San Diego State University San Diego California USA

Data-intensive applications like video processing and bioinformatics increasingly demand a high-performance and highly reliable storage system. Hard disk drive (HDD) has long been used as a standard storage device for most existing storage systems. Recently, NAND-flash memory based solid state drives (SSDs) are gradually exploited to replace HDDs in enterprise computing infrastructures due to their salient features such as high performance, low power consumption, and excellent shock-resistance. With rapid price decreasing and capacity increasing, flash SSD based disk arrays organized in some RAID structures become feasible and greatly needed. In this paper, we propose a new RAID4 architecture called SPD-RAID4 (Splitting Parity Disk - RAID4) for parallel SSD arrays. It splits the parity disk of a traditional RAID 4 array into configurable number of smaller ones. thus, multiple small parity SSDs operate in tandem with data SSDs to achieve a high performance and high level of reliability. We compare the performance of SPD-RAID4 with conventional RAID4 and RAID5 architectures by using both real-world traces and synthetic benchmarks. Experimental results demonstrate that in terms of mean response time SPD-RAID4 outperforms standard RAID5 structured SSD arrays by up to 20.3%. Compared with standard RAID4, SPD-RAID4 achieves a performance gain up to 40.6%.

关键词： Arrays Standards Reliability Time factors Flash memories Performance evaluation

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High Performance Database processing

High Performance Database Processing

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international conference on Advanced Information Networking and Applications (AINA)

作者： David Taniar Clayton School of Information Technology Monash University Clayton VIC Australia

the sizes of databases have seen exponential growth in the past, and such growth is expected to accelerate in the future, with the steady drop in storage cost accompanied by a rapid increase in storage capacity. Many years ago, a terabyte database was considered to be large, but nowadays they are sometimes regarded as small, and the daily volumes of data being added to some databases are measured in terabytes. In the future, petabyte and exabyte databases will be common. With such volumes of data, it is evident that the sequential processing paradigm will be unable to cope, for example, even assuming a data rate of 1 terabyte per second, reading through a petabyte database will take over 10 days. To effectively manage such volumes of data, it is necessary to allocate multiple resources to it, very often massively so. the processing of databases of such astronomical proportions requires an understanding of how high-performance systems and parallelism work. Besides the massive volume of data in the database to be processed, some data has been distributed across the globe in a Grid environment. these massive data centres are also a part of the emergence of Cloud computing, where data access has shifted from local machines to powerful servers hosting web applications and services, making data access across the Internet using standard web browsers pervasive. this adds another dimension to such systems. this talk, based on our recent published book [1], discusses fundamental understanding of parallelism in data-intensive applications, and demonstrates how to develop faster capabilities to support them. this includes the importance of indexing in parallel systems [2-4], specialized algorithms to support various query processing [5-9], as well as objectoriented scheme [10-12]. parallelism in databases has been around since the early 1980s, when many researchers in this area aspired to build large special-purpose database machines -- databases employing dedicated specialized

关键词： Distributed databases parallel processing Query processing Bioinformatics Algorithm design and analysis

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