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Data Management Mechanisms for IoT: Architecture, Challenges and Solutions

Data Management Mechanisms for IoT: Architecture, Challenges...

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international Multidisciplinary conference on Computer and Energy Science (SpliTech)

作者： Bassirou Diène Ousmane Diallo Joel J. P. C. Rodrigues EL Hadji M. Ndoye Ciprian Teodorov University of Assane Seck Ziguinchor Senegal Federal University of Piauí (UFPI) Teresina PI Brazil Instituto de Telecomunicações Portugal Lab-STICC UMR CNRS 6285 ENSTA Bretagne France

ISBN: (数字)9789532901054

ISBN: (纸本)9781728173634

the current traditional database management mechanisms and analytics architectures are not generally suitable for addressing the intrinsic characteristics of diversity, heterogeneity, large-scale, dynamic and large amount of data generated by the Internet of things (IoT) networks and various IoT applications needs. then, it is challenging to provide efficient IoT data storage and query processing mechanisms for meeting the requirements of applications. this paper identifies the most relevant characteristics and mechanisms of IoT data management and categorizes them. Moreover, a new four layers fog-based architecture using the distributed approach is proposed for providing a secure storage infrastructure and efficient real-time IoT data discovering with better latency. Finally, this work shows advances on IoT data management mechanisms, highlights their advantages and limits, and discusses the challenging open research issues that need to be focused for providing guidelines for new contributions.

关键词： Query processing Memory Distributed databases Real-time systems Internet of things Secure storage Guidelines

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Simulation Model for Controlling the processing of Information Packets by a NoC Router

Simulation Model for Controlling the Processing of Informati...

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Information, Control, and Communication Technologies (ICCT), international conference on

作者： Denis Kutuzov Alexey Osovsky Dmitriy Starov Nataliya Maltseva Vladimir Esaulenko dept. of Communication Astrakhan State Technical Universitet Astrakhan Russia dept. of Automated Information Processing and Control Systems Astrakhan State Technical Universitet Astrakhan Russia

this article describes the challenges of modeling switch fabric traffic that is part of NoC routers. Simulation is often used to validate a NoC design and identify potential performance bottlenecks before implementing hardware. Due to the distributed and complex network topology of routers, arbitration and routing algorithms, etc., timing, buffer queuing, and hence infrastructure performance are difficult to predict. Network traffic also generates application traffic in data processing nodes. When processing NoC traffic, the activity of IP cores is unstable and does not have stationarity, so it is very important to find traffic control mechanisms. Often, well-known models built on the basis of queuing theory do not always correctly reflect the connection request processing logic, do not take into account deadlocks and other features of the system functioning. An approach that can more accurately take into account the nuances of the switch is to build an agent-based model. To create it, we used the Mesa framework implemented in the Python programming language. the switch has small built-in buffers - one for each input. the model used a switch with 5 inputs and 5 outputs. the idea behind switch traffic management is to count how often there are transacts in the internal buffers that are directed to one exit. If they occur frequently enough, then the information flow is split and two or more outputs are given the same identifier to service such transacts in parallel.

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Efficiency Across Datasets: Insights into Video Compression Techniques

Efficiency Across Datasets: Insights into Video Compression ...

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Image processing and Capsule Networks (ICIPCN), international conference on

作者： A. Sreeram B. Umesh Chandra G. Sai Swetha Shilpa Bagade Electronics and Communication Engineering GRIET Hyderabad India

ISBN: (数字)9798350367171

ISBN: (纸本)9798350367188

In recent times, there has been notable progress in deep learning-based image compression, showcasing enhanced coding efficiency and subjective quality. However, comparatively less attention has been devoted to video compression employing deep neural networks. this paper introduces DeepLVCnet is a deep predictive video compression network that operates from end to end. With multiple framework theories, multiple scale arrangements, and a temporal context-adaptive entropy model, the method makes use of mode-selective uni-and bi-directional predictions. DeepLVCnet jointly compresses motion information and residual data through feature transformation layers within the multi-scale structure. A mode-selective architecture with uni-directional and bidirectional predictive modes is incorporated into DeepLVCnet, in contrast to earlier deep learning-based video compression techniques limited to P-frame or B-frame usage. Furthermore, utilizing temporal context information from reference frames during current frame coding, a unique temporal-context-adaptive entropy model is developed. this model is designed to enable parallel processing, offering computational and architectural advantages over autoregressive entropy models used in some CNN-based video compression methods. the overall objective is to enhance coding efficiency and subjective video enlargement quality through these innovations.

关键词： Training Technological innovation Image coding Computational modeling Video compression parallel processing Entropy

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Optimizing IoT Capabilities: Leveraging FPGA for Superior Performance, Efficiency and Security

Optimizing IoT Capabilities: Leveraging FPGA for Superior Pe...

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Emerging Technology (INCET), international conference for

作者： Gurdeep Singh Amanpreet Kaur Vaneeta Bhardwaj Shishir Shrivastava Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (数字)9798350361155

ISBN: (纸本)9798350361162

Nowadays IoT (Internet of things) is used everywhere, like homes, industry, automation, health sector, hospitality, smart cities, farming, tourism, self-driving cars etc. IoT is implemented successfully on many available hardware devices such as Microcontrollers, Arduino, Raspberry Pi, ASIC (Application-Specific Integrated Chip), FPGA (Field Programmable Gate Array) etc. Out of all these hardware platforms, FPGA is found to be more energy-efficient and the least power-consumable device. the use of FPGA with IoT is more reliable and effective in terms of power and energy saving. In this work, the integration of different technologies using IoT and FPGA is represented in the comparison table. the number of research works and publications on IoT using different hardware devices have been shown from year 2015 to 2023.

关键词： Performance evaluation Microcontrollers Smart cities Energy conservation parallel processing Hardware Internet of things

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5 Gbit/s real-time processing using π/4-shift DQPSK for bidirectional radio-over-fibre system

5 Gbit/s real-time processing using π/4-shift DQPSK for bid...

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international conference on Transparent Optical Networks

作者： Kai Habel Luz Fernandez del Rosal Stefan Weide Jonas Hilt Volker Jungnickel Robert Elschner Colja Schubert Felix Frey Johannes Karl Fischer Ronald Freund Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany

Future converged fixed-mobile networks need high-speed radio links in deployment scenarios where fibre is not available or too expensive. In this paper, we present a field-programmable gate array (FPGA)-based real-time transmission system using standard 10G Ethernet interfaces. the system comprises two parallel complex-valued data channels in each direction. Standard FPGAs and low-cost multi-channel analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs) have been used. For enhanced robustness and optimal usage of the power amplifier, π/4-shift differential quaternary phase-shift keying (DQPSK) modulation is used. All digital signal processing routines for synchronization, equalization, forward error correction etc. have been fully implemented and tested. Using a protocol analyzer, error-free bidirectional transmission of Ethernet frames at 5 Gbit/s is verified. Error-vector magnitude (EVM) values below -30 dB indicate that even higher speeds could be realized.

关键词： Synchronization Field programmable gate arrays Bit error rate Signal processing algorithms Boards Forward error correction Signal to noise ratio

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A multicore-aware von Neumann programming model

A multicore-aware von Neumann programming model

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international conference on Software Engineering and Applications (ICSOFT-EA)

作者： János Végh Zsolt Bagoly Ádám Kicsák Péter Molnár Faculty of Informatics University of Debrecen Debrecen Hungary PhD School of Informatics University of Debrecen Debrecen Hungary

An extension to the classic von Neumann paradigms is suggested, which -from the point of view of chip designers- considers modern many-core processors, and -from the point of view of programmers- still remains the classic von Neumann programming model. the work is based on the ideas that 1) the order in which the instructions (and/or code blocks) are executed does not matter, if some constraints do not force a special order of execution 2) a High Level parallelism for code blocks (similar to Instruction Level parallelism for instructions) can be introduced, allowing high-level out of order execution 3) discovering the possibilities for out of order execution can be done during compile time rather than runtime 4) the optimization possibilities discovered by the compile toolchain can be communicated to the processor in form of meta-information 5) the many computing resources (cores) can be assigned dynamically to machine instructions. It is shown that the multicore architectures could be transformed to a strongly enhanced single core processor. the key blocks of the proposal are a toolchain preparing the program code to run on many cores, a dispatch unit within the processor making effective use of the parallelized code, and also a much smarter communication method between the two key blocks is needed.

关键词： Computational modeling Multicore processing Hardware parallel processing Out of order Programming

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Advanced high speed parallel Frame Synchronizer for high data rate Indian Remote sensing satellite series

Advanced high speed Parallel Frame Synchronizer for high dat...

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international conference on Computers and Devices for Communication (CODEC)

作者： R. Srinivas P. V. V. Subba Rao L. Nithyanandan P. Naveen Kumar G. Umadevi Satellite Data Reception Systems National Remote Sensing Centre ISRO Hyderabad India Department of Electronics and Communication Engineering Pondicherry Engineering College Puducherry India Department of Electronics and Communication Engineering Osmania University Hyderabad India

ISBN: (纸本)9781467326193

the Video data from remote sensing satellite is transmitted serially frame after frame. To mark the beginning of video data a known unique code is embedded at the beginning of the video data frame. this is known as Frame Synchronizer code. Pseudo-Noise sequences are chosen as frame synchronizer codes as they are easy to generate, detect and have auto correlation property. Generally, for all Indian Remote sensing satellite series 127 bits Pseudo-Noise sequence is chosen as frame synchronizer code. On-board the satellite, the video data buffering is in serial fashion and for appropriate processing it is required to be formatted in data packets. Hence, data formatting is done onboard the satellite and then the Pulse Coded Modulated data is transmitted to ground station. the previous Indian Remote Sensing Satellites series has data rate of 105 Mbps. the Present data rate of Radar imaging satellite-1 (RISAT-1) is 640 MBps. In order to accommodate such high data rates in the limited bandwidths, the video data is transmitted in Right hand Circular Polarization (RHCP) and Left Hand Circular Polarization (LHCP). the QPSK modulation is used for video data transmission. Hence at such high data rates an advanced high speed frame synchronizer is required to cater to such high data rates. the advanced parallel processing technique of frame synchronism, detection and monitoring is unique as it doubles the operating frequency of the Frame synchronizer. Also with the same hardware, the frequency response of the hardware circuit can be doubled. If the maximum operating frequency is `f' Hz then using Advanced parallel Frame synchronizer technique, the operating frequency response is doubled to `2f' Hz using the same hardware chip. In this paper Advanced frame synchronizer circuit is been implemented and is put to use to archive video data from Indian Radar Imaging Satellite-1.

关键词： Advanced Frame synchronizer Pseudo-noise Sequence (PN sequence) Indian remote sensing satellites (IRS) Right hand circular polarization (RHCP) Left hand circular polarization (LHCP) Radar Imaging satellite (RISA T) video data Data transfer rates Synchronizer remote sensing satellites FRAMES Frame frequency response operating frequency maximum operating frequency

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Implementation of High-speed and High-Accuracy Convolutional Neural Network Accelerator for Target Detection Applications

Implementation of High-speed and High-Accuracy Convolutional...

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Innovative Trends in Information Technology (ICITIIT), international conference on

作者： Anandakumar Haldorai R Babitha Lincy M Suriya Minu Balakrishnan Centre for Future Networks and Digital Twin Sri Eshwar College of Engineering Coimbatore TamilNadu India

ISBN: (数字)9798350386813

ISBN: (纸本)9798350386820

Deep Convolutional Neural Network (CNN) for real-time applications heavily depends on computing efficiency. the efficiency of the CNN algorithm has been improved by modifying Convolutional Neural Network accelerator. thus, the proposed work development of improved CNN accelerator using Residue Number System (RNS) and implement in FPGA for performance investigation of throughput, latency, accuracy. the non-weighted nature of RNS makes it suitable for high-speed applications. As a result, it requires less space to house input feature maps and kernels. In addition to that, the proposed method will allow for parallel computation and required less power consumption. According to test results, the planned CNN accelerator can run the AlexNet at 165.4 frames per second, 200.5 GOPs per second at its max, and 22.5 GOPs per Watt. Additionally, it can be changed to support VGG-16 for complicated object recognition.

关键词： Power demand Object detection parallel processing throughput Real-time systems Convolutional neural networks Object recognition

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To BI or not to BI?

To BI or not to BI?

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Computers and Artificial Intelligence Technologies (CAIT), international conference on

作者： Adil Alizada Johan John thomas Mir Imaad Ali Kayvan Karim Mathematical and Computer Sciences Heriot Watt University Dubai UAE

ISBN: (数字)9798331530891

ISBN: (纸本)9798331530907

Suicide continues to be an issue in our society. Studies agree that it is best to deal with suicidal ideation in its early stages, and for this reason, researchers have been conducting experiments training different Neural Networks (NN) to detect it. Transformers are the dominant Neural Network architecture in the domain of Suicidal Ideation detection, being a robust solution for not only the proposed problem but for a wide variety of NLP problems. LSTM-CNN, one of the prominent architectures in the field is also proposed as a great solution. this study aims to evaluate the performance of BERT, RoBERTa, LSTM-CNN, and Bi-LSTM-CNN models for suicidal ideation detection. Our experiments indicated that BERT models have an edge over both LSTM-CNN and BI-LSTM-CNN models, scoring up to 0.986 accuracy on our test set. Furthermore, while directly comparing LSTM-CNN with Bi-LSTM-CNN, it was observed that the difference between the models isn’t significant. Our paper contributes to the domain by proving no advantage of using LSTM-CNN models over the Transformers.

关键词： Training Deep learning Filtering Image edge detection Computer architecture Bidirectional control Transformers Depression Natural language processing Encoding

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Hyaline: A Transparent Distributed Computing Framework for CUDA

Hyaline: A Transparent Distributed Computing Framework for C...

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international conference for Convergence of Technology (I2CT)

作者： Akshat Jain Owais Kazi Raviraj Joshi Shraddha Basantwani Yogita Bang Rahul Khengare Computer Engineering PICT Pune Computer Science IIT Madras

ISBN: (数字)9781538680759

ISBN: (纸本)9781538680766

the GPU usually handles the homogenous data parallel work, by taking advantage of its massive number of cores. In most of the applications, we use CUDA programming for utilizing the power of GPU. In data intensive high computational applications like neural networks, utilizing the GPU on a single machine is time consuming. Instead if multiple GPUs are used in a network the amount of time required will be significantly reduced. Traditionally to enable a set of program to be run in a distributed environment, programmer has to accordingly design components to make his system dynamic and resilient to changes in number of systems in cluster, which is a daunting task. this work distribution can be a poor solution as it may underutilize the GPUsIn our approach, we developed a framework which transparently distributes data parallel kernels across multiple GPUs in a distributed network. the programmer is responsible for developing a single data parallel kernel in CUDA while the framework automatically distributes the workload across an arbitrary set of CUDA enabled GPUs. Depending on current workload on GPUs and the amount of data to be processed optimal distribution is done. the goal is to maximally utilize the available resources with minimal programming complexity. the systems not compatible with CUDA can also utilize our solution. We expect our framework to reduce the processing time along with simplifying the task of programmers.

关键词： Graphics processing units Kernel Distributed databases Computational modeling Programming Task analysis Computer architecture

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