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A high-throughput, scalable solution for calculating frequent routes and profitability of New York taxis 15

A high-throughput, scalable solution for calculating frequen...

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Proceedings of the 9th ACM international conference on Distributed Event-Based Systems

作者： Amila Suriarachchi Shrideep Pallickara Colorado State University Fort Collins Colorado

ISBN: (纸本)9781450332866

processing complex queries on unbounded event streams in real-time, is a challenge for many data processing systems. these systems are expected to process data with reduced latency to generate real-time events, and at high throughput to minimize the required hardware. In this regard, Grand Challenge 2015 [6] focuses on evaluating two queries (frequent routes and profitable cells) in real-time with low latency and high throughput. these queries involve processing windows of thousands of records. Firstly, such processing demands efficient data structures and algorithms to minimize the processing overhead. Secondly, the system should partition data to evaluate them in parallel to make it *** this paper, we present a set of data structures that we designed to evaluate the aforementioned queries with O(log n) time complexity and a data partitioning technique to evaluate them in parallel. We then evaluate our solution on a single machine as well as in a distributed setting in a commodity cluster of machines over a 1Gbps LAN. We were able to process the frequent routes query with the 173 million trips dataset within 5 minutes with less than 4 millisecond latency and the profitable cells query with same dataset within 11 minutes with less than 5 millisecond latency.

关键词： real-time analytics time complexity event stream processing running median distributed event processing

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Design of Generic Floating Point Multiplier and Adder/Subtractor Units

Design of Generic Floating Point Multiplier and Adder/Subtra...

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international conference on Computer Modeling and Simulation, UKSIM

作者： Lamiaa Sayed Abdel Hamid Khaled Shehata Hassan El-Ghitani Mohamed ElSaid ECE Department Misr International University Cairo Egypt ECE Department Arab Academy for Science Technology and Maritime Transport Cairo Egypt ECE Department Ain Shams University Cairo Egypt

A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and used in the multiplier implementation. the new algorithm depends on dividing the multiplication operation into several smaller multiplications performed in parallel. the output from these multiplications is then manipulated in a manner to give the final result of the original multiplication operation. the adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm. In order to achieve high maximum, speed, both units were deeply pipelined. the design is written using VHDL code and mapped to Virtex2, Virtex4 and Virtex5 FPGAs. Both units can operate at more than 400 MHz on Virtex4.

关键词： Signal processing algorithms Field programmable gate arrays Frequency Neck Floating-point arithmetic Hardware Computational modeling Computer simulation Detectors Computer architecture

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A Naive-Bayesian Methodology to Classify Echo Cardiographic Images through SQL

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5th international conference on Knowledge, Information, and Creativity Support Systems

作者： Nandagopalan, S. Adiga, B. S. Sudarshan, T. S. B. Dhanalakshmi, C. Manjunath, C. N. Amrita Sch Engn Dept Comp Sci Si Engn Amrita Vishwa Vidyapeetham Bangalore Karnataka India Tata Consult Serv Parallel Comp Div Bangalore Karnataka India Amrita Sch Engn Dept Comp Sci & Engn Amrita Vishwa Vidyapeetham Bangalore Karnataka India Sri Jayadeva Inst Cardiovasc Sci & Res Dept Echocardiog Bangalore Karnataka India Sri Jayadeva Inst Cardiovasc Sci & Res Bangalore Karnataka India

ISBN: (纸本)9783642247873

Generally patient data in healthcare environments exist in relational databases. Classification of echocardiographic images is an important data mining task that helps hospitals without transferring the data in any form. this paper proposes a novel method to accomplish this task using naive Bayesian model via SQL. the proposed method has two phases. the first phase builds a knowledge base using many normal and abnormal subjects and the second phase uses this knowledge to categorize an unseen subject into appropriate class. the image features such as cardiac chamber dimensions (specifically Left Ventricle - LV), Ejection Fraction, Mitral valve (MV) orifice area, etc., are computed by first segmenting the image by employing advanced image processing techniques. For instance, to segment echo images we employ an efficient SQL based Fast K-Means algorithm combined with a greedy active contour algorithm for accurate boundary detection. Additional features such as textural, statistical, and histogram are computed and added to the classifier model by analyzing color Doppler echo images to strengthen the classifier accuracy. Our SQL based naive Bayesian classifier model is built with 7 schema, simple yet efficient SQL queries and thus providing an accurate classification of patients as normal or abnormal. the model is trained with 112 patient data and we believe that the clinical decision is simplified and can happen on-the-fly. Experimental results presented in this paper show an increased accuracy of 87.48% against the other state-of-the art segmentation and classification methods reported.

关键词： Echocardiographic image Naive-Bayseian Classification K-Means Segmentation SQL Active Contour

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Locality-sensitive operators for parallel main-memory database clusters

Locality-sensitive operators for parallel main-memory databa...

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international conference on Data Engineering

作者： Wolf Rödiger Tobias Mühlbauer Philipp Unterbrunner Angelika Reiser Alfons Kemper thomas Neumann Technische Universitat Munchen Munich Germany Snowflake Computing Inc. San Mateo CA

the growth in compute speed has outpaced the growth in network bandwidth over the last decades. this has led to an increasing performance gap between local and distributed processing. A parallel database cluster thus has to maximize the locality of query processing. A common technique to this end is to co-partition relations to avoid expensive data shuffling across the network. However, this is limited to one attribute per relation and is expensive to maintain in the face of updates. Other attributes often exhibit a fuzzy co-location due to correlations with the distribution key but current approaches do not leverage this. In this paper, we introduce locality-sensitive data shuffling, which can dramatically reduce the amount of network communication for distributed operators such as join and aggregation. We present four novel techniques: (i) optimal partition assignment exploits locality to reduce the network phase duration; (ii) communication scheduling avoids bandwidth underutilization due to cross traffic; (iii) adaptive radix partitioning retains locality during data repartitioning and handles value skew gracefully; and (iv) selective broadcast reduces network communication in the presence of extreme value skew or large numbers of duplicates. We present comprehensive experimental results, which show that our techniques can improve performance by up to factor of 5 for fuzzy co-location and a factor of 3 for inputs with value skew.

关键词： Bandwidth Partitioning algorithms Distributed databases Correlation Database systems Algorithm design and analysis

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Modeling and Control of Temperature Dynamics In Induction Furnace System

Modeling and Control of Temperature Dynamics In Induction Fu...

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IEEE international conference on System Engineering and Technology

作者： Rina Ristiana Arief Syaichu-Rohman Pranoto H. Rusmin Mineral Processing Unit-LIPI Jl. Ir. Sutami Km15 Tanjung Bintang School of Electrical Engineering and Informatics Institut Teknologi Bandung

ISBN: (纸本)9781467367141

this paper explains modeling and control of temperature dynamics on induction furnace. Induction furnace is used for melting metal to process raw material scrap into steel ferrit rate 0.22 wt% carbons. the dynamics response of the induction furnace temperature affects the resulting product. therefore, the controller of temperature dynamics is required to produce the desired process response. the induction furnace systems consist of electrical and thermal system dynamics. the dynamics of the electrical system represents the induction furnace system in the form of an electric circuit i.e. fed current inverter with a parallel resonant circuit. Meanwhile, the thermal system dynamics represents the thermal energy transfer process, which is developed with the principle of energy balance, including heat generated energy and heat loss. Induction furnace system dynamics is modelled in an order 2 system, with a time constant coil 1000 times faster than time constant temperature. thus, by ignoring the time constant coil, induction furnace system dynamic model can be transformed into a first order nonlinear system. then, linear system can be obtained by making a replacement variable. Induction furnace temperature control has been implemented by adjusting the PWM to control the input power to the induction furnace. PI controller is designed in three cases, namely linear model with linear PI controller, saturated linear model with linear PI controller, and saturated linear model with anti-windup PI controller. Each case is simulated by Simulink. To get the appropriate specifications, the temperature should be controlled at 912 Celsius degree. the best results can be achieved with maximum overshoot is 7% and the rise time is 2.9 seconds.

关键词： Induction furnace parallel resonant circuit Saturated linear model Anti-windup PI INDUCTION FURNACES PI control energy balance System dynamics Modeling Temperature control PULSE RISE TIME linear models maximum overshoot Standing Orders Electrical systems

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High-Speed, Area-Efficient three-Operand Pipelined Adder

High-Speed, Area-Efficient Three-Operand Pipelined Adder

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Communication, Computing and Industry 4.0 (C2I4), international conference on

作者： Uzma Sultana Shreya Sagar S Veena.M.B Department of Electronics BMS College of Engineering Bangalore India

ISBN: (数字)9798350379884

ISBN: (纸本)9798350379891

In high-speed arithmetic circuits, adder efficiency is crucial for system performance. Common adders like Carry Skip, Han-Carlson, and Kogge Stone aim to optimize delay and area but still struggle to balance speed, area, and power. this paper introduces a new three-operand pipelined adder, replacing conventional parallel prefix logic with a streamlined pipelined method. the design combines an adder and subtractor in one unit, using modular logic to handle both functions. Pipelining allows continuous data processing, increasing throughput and reducing critical path delay. this three-operand pipelined adder achieves significant area and delay improvements over traditional designs. Using fewer logic gates and connections makes the design more compact and improves its performance. Simulations and synthesis validate the proposed design's effectiveness, showing major improvements in speed and area, making it valuable for high-speed, area-limited VLSI applications.

关键词： System performance Very large scale integration Logic gates throughput Silicon Delays Logic Adders Arithmetic Pipeline processing

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A CNN Accelerator on FPGA with a Flexible Structure

A CNN Accelerator on FPGA with a Flexible Structure

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international conference on Computational Intelligence and Applications (ICCIA)

作者： Dan Shan Guotao Cong Wei Lu Department of Electronic Engineering Dalian Neusoft University of Information Dalian P. R. China School of Control Science and Engineering Dalian University of Technology Dalian P. R. China

ISBN: (数字)9781728160429

ISBN: (纸本)9781728160436

Most of the existing convolutional neural networks (CNNs) are based on PC software, which cannot meet the real-time, low power and miniaturization requirements of the systems. In this paper, a CNN accelerator with flexible structure based on Field-Programmable Gate Array (FPGA) is proposed to achieve recognition of MNIST handwritten numeric characters. the system adopts deep pipeline processing and optimizes inter-layer and intra-layer parallelism from two levels of coarse and fine granularity. In view of the similarity of convolution structure, this design adopts structured circuit, which can easily expand the number of layers and neurons. the classification throughput and inter-layer data throughput capability can be improved by rationally organizing the internal memory resources of the FPGA. Compared with the general CPU, it achieves 3 times acceleration at 50MHz frequency, while the power consumption is only 2% of the CPU. Finally performance and power consumption are compared with other accelerators by VGG16.

关键词： Convolution Neurons Field programmable gate arrays parallel processing Kernel Computer architecture System-on-chip

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AUModel:A Conceptual model for Adaptive Software

AUModel:A Conceptual model for Adaptive Software

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2014 IEEE 5th international conference on Software Engineering and Service Science

作者： Hui Liu Bo Ding Dianxi Shi Huaimin Wang National Key Laboratory for Parallel and Distributed Processing College of Computer ScienceNational University of Defense Technology

Pervasive software should be able to adapt itself to the changing environments and user ***,it will bring great challenges to the software engineering *** paper proposes AUModel,a conceptual model for adaptive software,which takes adaptability as an inherent feature and can act as the foundation of the engineering *** introducing AUModel,the reuse of software adaptation infrastructure as well as the separation of adaptation concerns are enabled,which can facilitate both the development and maintenance of adaptive *** paper also presents our initial attempts to realize this model,including a middleware prototype to support this model and an application to validate its effectiveness.

关键词： pervasive computing adaptive software middleware

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Distributed real-time processing for humanoid robots

Distributed real-time processing for humanoid robots

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IEEE international conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： T. Matsui H. Hirukawa Y. Ishikawa N. Yamasaki S. Kagami F. Kanehiro H. Saito T. Inamura Digital Human Research Center AIST Tokyo Japan Research Institute of Intelligent Systems AIST Tsukuba Japan Department of Computer Science University of Tokyo Tokyo Japan Department of Information and Computer Science Keio University Yokohama Japan

A humanoid robot is a real-time system controlled by a complex computer system that requires huge computing power for perception and planning, high energy efficiency for self-contained control, reduction of physical dimensions, and high reliability. this paper proposes a distributed architecture for the humanoid robot control substituting conventional centralized control architectures. In addition to the parallelism that provides scalable computing power at low clock namely at low energy, the distributed architecture contributes to reliable operations by replacing many fragile analog signal wires with a digital network with redundant routes. In order to accomplish a real-time control over the network, RMTP (responsive multi-threaded processor) for parallel and real-time computation has been newly designed. RMTP can synchronize more than thirty nodes distributed over a robot body in less than 5 micro second with a real time network called the responsive link (RL). architectures of RMTP, RL and Linux-based real-time system software are presented.

关键词： Humanoid robots Computer architecture Real time systems Control systems Physics computing Power system reliability Centralized control Computer networks Concurrent computing Power system planning

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Development of an Intelligent Intrusion Detection Model using an Ensemble of Deep Learning Paradigm

Development of an Intelligent Intrusion Detection Model usin...

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IEEE international conference on Emerging & Sustainable Technologies for Power & ICT in a Developing Society (NIGERCON)

作者： Olamatanmi Josephine Mebawondu Tajudeen Adeleke Badmos Olufunsho D. Alowolodu Jacob Olorunshogo Mebawondu Department of Computing Afe Babalola University Ado-Ekiti Ado-Ekiti Nigeria Department of Computer Science Faculty of Information Technology Federal Polytechnic Nasarawa Nasarawa Nigeria Department of Cyber Security Federal University of Technology Akure Nigeria Department of Computer Science Federal Polytechnic Naasrawa Nasarawa Nigeria

ISBN: (数字)9798331542559

ISBN: (纸本)9798331542566

the internet's advent has permeated every aspect of our lives, resulting in an explosion of information generation and management. Deep learning, as an Artificial Intelligence (AI) function, mimics human intelligence in data processing for decision-making. Deep learning (DL) encompasses a variety of machine learning techniques where unsupervised and supervised feature learning can be implemented across multiple layers in hierarchical architectures. Combining deep learning techniques can mitigate the weaknesses of individual methods. this research aims to integrate deep learning techniques to develop an intelligent intrusion detection model. the combined models yield a Network Intrusion Detection System (NIDS) with superior performance compared to individual techniques. the results demonstrate that the ensemble model achieves an accuracy of 79%, surpassing single deep learning models.

关键词： Deep learning Representation learning Humanities Human intelligence MIMICs Decision making Network intrusion detection Data processing Explosions Ensemble learning

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