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Performance and Power Analysis of High-Density Multi-GPGPU architectures: A Preliminary Case Study

Performance and Power Analysis of High-Density Multi-GPGPU A...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yuxiang Gao Saeed Iqbal Peng Zhang Meikang Qiu Global Solution Engineering Group Dell Inc. Round Rock United States Biomedical Engineering Department Stony Brook University Stony Brook United States Computer Science Department Pace University New York United States

A system architecture with high-density general purpose graphic processing unit (GPGPU) is emerging as a promising solution that can offer high compute performance and performance-per-watt for building cluster supercomputers. the raw compute power of these heterogeneous systems greatly exceeds the current prevailing homogenous systems, motivating their rapid adoption. these heterogeneous systems do however increase the complexity of developing parallel applications and there is a need to investigate the compute performances and associated power consumption of common benchmarks and scientific computing applications. In this paper, we present the performance and power studies through using the Dell C4130 server that integrates up to 4 GPGPU cards and NVIDIA GPGPU K80 is used. the high performance Linpack (HPL) and molecular dynamics (MD) simulators including NAMD, LAMMPS and GROMACS are tested. through comparing 4-K80 and 2-Xeon E5-2690 v3 systems, we show that: (1) for HPL tests, the 4- GPU server delivers up to 7 TFLOPS that is 9 times faster than the 2-CPU system and its power efficiency is 4 GFLOPS per Watt, (2) for MD tests, NAMD on 4-GPU server achieves 7.8 times speedup and it uses 2.3 times power consumption compared to 2-CPU system, and LAMMPS achieves 16 times speedup and it uses 2.6 times power consumption, and GROMACS achieves 3.3 times speed up and it uses 2.6 times power consumption. these preliminary results demonstrated that the novel high-density multi-GPGPU architecture offers high performances for computing intensive applications and molecular simulators with superior power efficiencies in a space efficient design. In future, such heterogeneous architecture could be a powerful alternative solution for next generation supercomputer systems.

关键词： Servers Power demand Computer architecture Graphics processing units Cooling Benchmark testing

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Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL

Research on Mahalanobis Distance Algorithm Optimization Base...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Qingchun Xie Yunquan Zhang Haipeng Jia Yongquan Lu High Performance Computing Center Communication University of China Beijing China Chinese Academy of Sciences Institute of Software Beijing China Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9781479961245

Mahalanobis distance algorithms has been widely used in machine learning and classification algorithms, and it has an important practical significance in improving the performance of some applications through GPU, especially in some applications with high real-time demand. However, due to the complexity of the GPU hardware architectures, how to complete the algorithm optimization and achieve high performance portability on different GPU platforms is still a hard work. the redundant calculation of traditional Mahalanobis distance algorithm is very large and is hard to implement parallel. In this paper, we not only throw light on the universal ways to properly map mature algorithms to GPU devices to implement the Mahalanobis distance, such as fixed number of workgroups and vectorization, but also put forward five valuable methods of performance optimization on heterogeneous computing platforms, such as two-dimension NDRange workgroup arrangement, Uberkernel, binary reduction with the help of LDS register in one workgroup. Furthermore, We also demonstrate the high performance of our implementation by comparing it with a well-optimized CPU version from OpenCV library. Experimental results show that speedup reaches up 10.59 times on NVIDIA GPU C2050, 8.55 times on AMD HD5850 and 16.08 times on HD7970. the last experimental results verified the effectiveness of optimization methods which we proposed.

关键词： Graphics processing units Instruction sets Synchronization Optimization Vectors Zinc Computer architecture

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Optimizing Web Browser on Many-Core architectures

Optimizing Web Browser on Many-Core Architectures

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IEEE international conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Lingjun Fan Weisong Shi Shibin Tang Chenggang Yan Dongrui Fan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Wayne State University Detroit USA

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. this leads to more and more performance requirements of a Web browser, for which user experience is very important. this situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.

关键词： Browsers HTML Web pages Layout Multicore processing System-on-a-chip

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An Empirical Study for the GPT-Based LLM in Paper Similarity Measurement

An Empirical Study for the GPT-Based LLM in Paper Similarity...

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Electronic Communication and Artificial Intelligence (IWECAI), international Workshop on

作者： Jinglin Yang College of Information Science and Engineering/ College of Artificial Intelligence China University of Petroleum (Beijing) Beijing China

ISBN: (数字)9798350386943

ISBN: (纸本)9798350386950

the Transformer model, with its core self-attention mechanism and encoder-decoder architecture, offers enhanced parallel computing capabilities and extended contextual memory. It has led to groundbreaking advancements in tasks such as machine translation and text generation. the development of Transformer models has also spurred the emergence of large language models like GPT. In theory, GPT models should have superior processing capabilities and flexibility in NLP tasks compared to conventional Transformer. However, there is a lack of research comparing the actual performance differences between them.. In this work, we bridge this gap by a systematical study of text similarity evaluation between ChatGPT and conventional Transformer. To this end, we propose an innovative paper similarity measurement to experimentally and comparatively analyze the performance differences. In this study, we collected paper data from public paper dataset and categorized it according to topic-based standards. Using the categorized dataset as a benchmark, we analyzed the similarity assessment results of comparison paper data. Additionally, we introduced a custom GPT scoring standard to evaluate paper similarity, further comparing the accuracy, interpretability, and stability of Transformerand GPT models.

关键词： Training Accuracy Computational modeling Stability criteria Transformer cores parallel processing Transformers

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Self-hosted placement for massively parallel processor arrays

Self-hosted placement for massively parallel processor array...

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IEEE international conference on Field-Programmable Technology (FPT)

作者： Graeme Smecher Steve Wilton Guy G. F. Lemieux University of British Columbia Vancouver BC Canada

We consider the placement problem as part of the CAD flow for a massively parallel processor arrays (MPPAs). In contrast to traditional placers, which operate on a workstation with one or several cores and are able to take advantage of parallelism to a limited degree, we investigate running the placer on the target architecture itself. As the number of processor elements (PEs) in such a device scale, so too does the computational power available to the placer. this natural scaling helps avoid the long runtimes that afflict FPGA flows. In this paper, we propose a distributed placer suitable to run on a MPPA. this placer takes advantage of local interconnect fabric, and may be efficiently coded on a simple, RISC-like core. We investigate the performance of this placer and compare it to traditional, simulated annealing-based placers using both unrealistic (but nearly optimal) and realistic (but suboptimal) annealing schedules. On a simulated 32 × 32 = 1024-core MPPA, the proposed algorithm furnishes placements within 5 % of the optimal placement quality a level competetive with the realistic, traditional placer. To do so, the distributed placer requires each PE to consider 1/256 th as many swaps as the traditional placer, a computational advantage which scales favourably as the number of cores on the MPPA increases.

关键词： Field programmable gate arrays Simulated annealing Clustering algorithms Silicon Logic arrays Workstations parallel processing Runtime Fabrics Distributed computing

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Bi-Transfer: A Data Packet Allocation Module with Chaining Transmission Mode

Bi-Transfer: A Data Packet Allocation Module with Chaining T...

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international conference on Computer and Communications (ICCC)

作者： Zerun Li Sen Yang Yu Wang Lirui Chen Yang Guo Zuocheng Xing College of Computer NUDT Changsha China

ISBN: (数字)9781728147437

ISBN: (纸本)9781728147444

With the increasing performance requirements of network data interaction on chip, the traditional Direct Memory Access (DMA) often performs with low efficiency of multi-module collaboration due to the competition of bus control, thereby reducing the throughput rate of the bus. Aiming at the working characteristics of inter-core communication and data interaction between multiple modules, this paper designs a packet transmission module Bi-Transfer that supports bidirectional data flow between multiple modules It also realizes chaining transmission of input and output data in parallel with various configuration modes and flexible data scheduling modes. this module can complete the functions of data movement, inter-core communication, task management, etc., and use descriptors to link load data packets to uniformly conFigure the data interaction mode of the on-chip network. In the experimental stage, function planning and code design are carried out first, then the timing simulation and data recording are described. Finally, the performance characteristics of this new data interaction module are discussed. According to statistical observations, increasing the number of channels in the design module can significantly increase the bandwidth of the bus. Under the given clock frequency, bus width and data transmission requirements, the bus operating bandwidth in the four-channel working mode can reach up to 4690 MB/s at most, which is nearly 400 MB/s beyond the ordinary DMA bus bandwidth. In the case of fewer channels, this module can fulfill the data scheduling requirements of most applications and provide the data moving function of ordinary DMA.

关键词： Scheduling algorithms Task analysis Bandwidth Data transfer Multicore processing Delays Scheduling

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parallel multi-scale CNN for image denoising 19

Parallel multi-scale CNN for image denoising

引用

Proceedings of the 5th international conference on Communication and Information processing

作者： Taoling Zhao Yi Zhong Yuanli Wang Wuhan University of Technology Wuhan Hubei

ISBN: (纸本)9781450372589

Deep learning has achieved outstanding performance in the field of image processing. Inspired by the inception model, we propose a deep neural network convolving simultaneously at two different scales. We utilize the convolution kernel of different sizes to carry out the convolution, which can obtain the features of the image at different scales. the features of the output are no longer uniformly distributed, but converge the features with strong correlation. Batch normalization (BN) and residual learning (RL) are utilized to speed up the training process as well as enhance the denoising ability of model. the experimental results of three salt-and-pepper noise levels based on the public dataset BSDS500 show that the newly proposed method can obtain significantly superior performance than current state-of-the-art approaches and higher peak signal to Noise Ratio (PSNR) in salt-and-pepper noise removal.

关键词： feature extraction at different scales residual learning inception model batch normalization image denoising

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Using rCUDA to Reduce GPU Resource-Assignment Fragmentation Caused by Job Scheduler

Using rCUDA to Reduce GPU Resource-Assignment Fragmentation ...

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IEEE international conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Pak Markthub Akihiro Nomura Satoshi Matsuoka Tokyo Institute of Technology Tokyo JAPAN

In heterogeneous supercomputers such as TSUBAME2.5, GPUs on some nodes in GPU batch queues are left idle even though there are jobs waiting in the queues, this is caused by GPU resource-assignment fragmentation problem. For example, in the case that each node has three GPUs like TSUBAME2.5's, if a node has already been assigned to a job requesting two GPUs per node, that node cannot be assigned to another job requesting more than one GPU per node until the ongoing job finishes, hence, one GPU is left idle on that node. We examine this problem on TSUBAME2.5's GPU batch-queue system and present a scheduling algorithm that assigns rCUDA (a remote CUDA execution technology) to some processes of some jobs. Because rCUDA allows jobs to utilize the idle GPUs, the proposed scheduling algorithm can alleviate the problem. Using a job pattern obtained from a scheduler log of a TSUBAME2.5's GPU queue, our simulation shows that the proposed algorithm can decrease jobs' lifetime (from the time when a job arrives until finishes) by about 5% on average. Moreover, it can reduce the average number of idle GPUs by about 15%. Also, even reducing the number of nodes serving jobs by around 4%, the proposed algorithm can maintain the average jobs' lifetime around the same as the scheduling algorithm currently used in the TSUBAME2.5's GPU queue.

关键词： Graphics processing units Servers Bandwidth Data transfer Scheduling algorithms Data models Scheduling

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A Research on Minisat Using Coarse-grained parallel Technique Based on Multi-core and Multi-platform

A Research on Minisat Using Coarse-grained Parallel Techniqu...

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2017 5th international conference on Machinery,Materials and Computing Technology(ICMMCT 2017)

作者： Junjie Zhu Jingfei Jiang Xiaocheng Luo Yong Dou National Laboratory of Parallel and Distributed Processing National University of Defence Technology

In this paper, we make a research on a widely-used SAT solver, Minisat, aiming to improve its performance using coarse-grained parallel method on multi-core and multi-platform. Firstly, we parallel the Minisat by mean of Open MP and test its performance with different threads by running a test set consisting of 2000 SAT problems on an X86 computer. Besides, a scheduling strategy with time sequence is added to the process and achieves a better speed-up ratio. then, we move the algorithm to an ARM computer and repeat the same process, finding that the performance of Minisat on X86 is better than that on ARM, but ARM platform has a better scale effect than X86 platform when running at full load and is able to perform better than X86 when they have the same hardware configuration.

关键词： Minisat solver coarse-grained multi-core multi-platform

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the Improved Frog Leaping Algorithm for Photovoltaic Array Parameter Identification

The Improved Frog Leaping Algorithm for Photovoltaic Array P...

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Clean Energy and Electric Power Engineering (ICCEPE), international conference on

作者： Wang Yao Zhong Chen Zhonglin Xu Yongkang Wu Changsha University of Science and Technology Changsha China

ISBN: (数字)9798350390315

ISBN: (纸本)9798350390322

During the process of photovoltaic array parameter identification, the use of the shuffled frog-leaping algorithm may encounter the issue of getting trapped in local optima. therefore, this paper proposes an improved hybrid shuffled frog-leaping algorithm-based method for photovoltaic array parameter identification. To tackle these issues, an improved mixed frog-leaping algorithm is proposed. the algorithm incorporates a mixed frog-leaping approach to introduce an asynchronous time-varying learning factor. this enhancement aims to improve the learning capability and search speed of the global optimal individual while maintaining algorithm convergence. By conducting comparative simulation experiments with the original hybrid shuffled frog-leaping algorithm, the results demonstrate that the improved algorithm enhances the identification speed and accuracy of the parameters in the photovoltaic cell single diode model. this improvement brings practical utility to the algorithm's application.

关键词： Photovoltaic systems Green energy Parameter estimation Accuracy Photovoltaic cells parallel processing Power systems Particle swarm optimization Optimization Convergence

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