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Research and Implementation of Binocular Image Stitching Algorithm Based on FPGA

Research and Implementation of Binocular Image Stitching Alg...

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Computer Vision, Image and Deep Learning (CVIDL), international conference on

作者： Zhenhui Yao Dingfeng Yu Weizhi Geng Hongfeng Zhang Yidong Xu Wei Xue Yantai Research Institute Harbin Engineering University Yantai China Wuhan Second Ship Design and Research Institute Wuhan China

ISBN: (数字)9798350373820

ISBN: (纸本)9798350373837

the underwater environment is complex and variable. Light propagation is affected by multiple factors, such as water absorption and scattering. this often results in a lack of brightness in underwater images, which can hinder the extraction of image features and affect the matching of feature points between subsequent images. Given the aforementioned issues, this paper proposes the use of the FPGA platform in conjunction with the ORB algorithm to enhance the original feature extraction and descriptor generation algorithm. the goal is to improve the effectiveness of the feature extraction algorithm under varying light intensities. Additionally, a new 64-bit descriptor is designed using the parallelism of the FPGA. False matching points are removed through statistical analysis, ultimately achieving feature matching between two underwater images.

关键词： Deep learning Concurrent computing Statistical analysis Scattering parallel processing Feature extraction Real-time systems

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Research on Trust Evaluation Model for Vehicle-to-Grid Interaction Based on Zero Trust Architecture

Research on Trust Evaluation Model for Vehicle-to-Grid Inter...

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Information Science, parallel and Distributed Systems (ISPDS), international conference on

作者： Nankai Zhou Shenglong Ji Qingmei Mao North China University of Technology Beijing China Qianxin Technology Group Co. LTD

ISBN: (数字)9798350352719

ISBN: (纸本)9798350352726

During vehicle-to-grid (V2G) interactions, information is transmitted across multiple platforms, posing significant security risks to both information transmission and network boundaries. Traditional evaluation techniques, which rely on fixed permission assignments and predefined rules, struggle to adapt to scenarios characterized by a large number of vehicles, frequent changes in network topology, and diverse service demands. this paper proposes a trust evaluation model based on zero trust architecture. By introducing multidimensional user attribute sets, platform attribute feature sets, and user recommendation attributes, the model dynamically evaluates the trustworthiness of users and platforms. It uses trust values to dynamically authorize access subjects and assess platform reliability. this approach enhances the system's ability to identify malicious behavior and improves the security of data resources and transmission in V2G interactions. Experimental results indicate that the proposed zero trust-based trust evaluation model significantly enhances the security and dynamic responsiveness of V2G interactions.

关键词： Vehicle-to-grid Technological innovation Network topology Data security Evaluation models Information processing Zero Trust

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Towards massively parallel simulations of massively parallel high-performance computing systems 12

Towards massively parallel simulations of massively parallel...

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Proceedings of the 5th international ICST conference on Simulation Tools and Techniques

作者： Robert Birke German Rodriguez Cyriel Minkenberg IBM Research -- Zurich Rüschlikon Switzerland

ISBN: (纸本)9781450315104

the power of high-performance computing (HPC) is applied to simulate highly complex systems and processes in many scientific communities, e. g. in particle physics, weather and climate research, bio-sciences, materials science, pharmaceutics, astronomy, or *** HPC systems are so complex that the design of such a system, including architecture design space exploration and performance prediction, requires HPC-like simulation capabilities. To this end, we developed an Omnest-based simulation environment that enables studying the impact of an HPC machine's communication subsystem on the overall system's performance for specific *** the scale of current high-end HPC systems is in the range of hundreds of thousands of processing cores, full system simulation---at an abstraction level that still maintains a reasonably high level of detail---is infeasible without resorting to parallel simulation, the main limiting factors being simulation run time and memory *** describe our experiences in adapting our simulation environment to take advantage of the parallel distributed simulation capabilities provided by Omnest. We present results obtained on a many-core SMP machine as well as a small-scale InfiniBand ***, we ported our simulation environment, including Omnest itself, to the massively parallel IBM Blue Gene®/P platform. We report results from initial experiments on this platform using up to 512 cores in parallel.

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FPGA Implementation of 32-Bit parallel LMS Adaptive Beamforming Architecture using Two 8-Bit Stages

FPGA Implementation of 32-Bit Parallel LMS Adaptive Beamform...

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international conference on Computing and Networking Technology (ICCNT)

作者： Mohini R. Damodar Yogita Vaidya Electronics and Telecommunication VLSI & Embedded system COEP Technological university Pune India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this research project analyses a hardware pipelined reduced complexity parallel least mean square (RC-pLMS) implementation for adaptive beamforming. the composite of every single stage of defects in RC-pLMS, which is composed of two massively parallel, least mean square (LMS) phases, produces the overall error signal (pLMS). By removing the second independent weight set, the pLMS has been further reduced in size, ending in a less complex pLMS architecture (RC-pLMS). Our proposed RCpLMS algorithm (DRC-pLMS) will utilise a pipelined hardware architecture because to this approach alongside the delay and sum relaxation approach. Synthesise and implementation outcomes show that the recommended design delivers a maximum operational frequency and its take maximum resource utilisations. the objective of this study is to improve efficiency by switching the DRC-pLMS design with two 8-bit input levels. At the end, this work was translated into Verilog HDL, produced on a Xilinx Vertex-5 FPGA, and all the parameters related to area, delay, and power were compared.

关键词： Frequency synthesizers Array signal processing Adaptive algorithms Mean square error methods Hardware Delays Hardware design languages Field programmable gate arrays Adders Convergence

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Unbalanced FIFO sorting for FPGA-based systems

Unbalanced FIFO sorting for FPGA-based systems

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Rui Marcelino Horácio C. Neto João M. P. Cardoso Ualg Faro Portugal UTL IST Lisboa Portugal University of Porto FEUP/DEI Porto Portugal

ISBN: (纸本)9781424450909

Sorting is an important operation in a myriad of applications. It can contribute substantially to the overall execution time of an application. Dedicated sorting architectures can be used to accelerate applications and/or to reduce energy consumption. In this paper, we propose an efficient sorting unit aiming at accelerating the sort operation in FPGA-based embedded systems. the proposed sorting unit, named Unbalanced FIFO Merge Sorting Unit, is based on a FIFO merger implementation and is easily scalable to handle different data-set sizes. We show results of the proposed sorting unit when isolated and when integrated in a software/hardware solution. When using a Xilinx Virtex-5 SX50T FPGA device, the logic resources for a 32 K-word machine is lower than 1%, and the block RAM usage is about 22%. When compared to a quicksort pure software implementation, our Sorting Unit provides speed-ups from 1.2x to 50x and about 20x when isolated and when integrated in a software/hardware solution, respectively.

关键词： Sorting Hardware Field programmable gate arrays Acceleration Embedded system Corporate acquisitions Signal processing algorithms Computer architecture Energy consumption Logic devices

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Tangram: High-Resolution Video Analytics on Serverless Platform with SLO-Aware Batching

Tangram: High-Resolution Video Analytics on Serverless Platf...

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international conference on Distributed Computing Systems

作者： Haosong Peng Yufeng Zhan Peng Li Yuanqing Xia School of Automation Beijing Institute of Technology Beijing China School of Computer Science and Engineering The University of Aizu Aizuwakamatsu Japan

ISBN: (数字)9798350386059

ISBN: (纸本)9798350386066

Cloud-edge collaborative computing paradigm is a promising solution to high-resolution video analytics systems. the key lies in reducing redundant data and managing fluctuating inference workloads effectively. Previous work has focused on extracting regions of interest (RoIs) from videos and transmitting them to the cloud for processing. However, a naive Infrastructure as a Service (IaaS) resource configuration falls short in handling highly fluctuating workloads, leading to violations of Service Level Objectives (SLOs) and inefficient resource utilization. Besides, these methods neglect the potential benefits of RoIs batching to leverage parallel processing. In this work, we introduce Tangram, an efficient serverless cloud-edge video analytics system fully optimized for both communication and computation. Tangram adaptively aligns the RoIs into patches and transmits them to the scheduler in the cloud. the system employs a unique “stitching” method to batch the patches with various sizes from the edge cameras. Additionally, we develop an online SLO-aware batching algorithm that judiciously determines the optimal invoking time of the serverless function. Experiments on our prototype reveal that Tangram can reduce bandwidth consumption and computation cost up to 74.30 % and 66.35 %, respectively, while maintaining SLO violations within 5 % and the accuracy loss negligible.

关键词： Costs Accuracy Visual analytics Prototypes Bandwidth parallel processing Inference algorithms

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Prediction of mechanical properties of hot-rolled steel based on multi-channel convolutional neural network 23

Prediction of mechanical properties of hot-rolled steel base...

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Proceedings of the 2023 5th international conference on Internet of things, Automation and Artificial Intelligence

作者： Zhengzhong Wang Shengdong Wang Kai Zhang Xingchang Tang Yichao Wang Jiugang Group Carbon Steel Sheet Factory China State Key Laboratory of Advanced Processing and Recycling of Nonferrous Metals Lanzhou University of Technology China College of Computer and Communication Lanzhou University of Technology China

ISBN: (纸本)9798400716485

A multi-channel parallel convolutional neural network model is proposed to predict the mechanical properties of hot-rolled steel by chemical content and process parameters. the innovative contribution of this paper is to propose an improved Gramian Angular field method in the field of steel performance prediction, which converts the original data into a two-dimensional image matrix and introduces new features. Compared with the traditional convolutional neural network model, the multi-channel parallel convolutional neural network uses private blocks to decouple data and public blocks to integrate key data, which effectively improves the prediction accuracy of the model. Experiments in this paper show that the optimal hyperparameter structure model proposed in this paper has higher prediction accuracy than similar models proposed in other literatures.

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Enhancing parallelization with OpenMP through Multi-Modal Transformer Learning

Enhancing Parallelization with OpenMP through Multi-Modal Tr...

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international conference on Computer Engineering and Applications (ICCEA)

作者： Yuehua Chen Huaqiang Yuan Fengyao Hou Peng Hu Dongguan University of Technology Dongguan China Institute of High Energy Physics Chinese Academy of Sciences Beijing China Spallation Neutron Source Science Center Dongguan China

ISBN: (数字)9798350386776

ISBN: (纸本)9798350386783

the popularity of multicore processors and the rise of High Performance Computing as a Service (HPCaaS) have made parallel programming essential to fully utilize the performance of multicore systems. OpenMP, a widely adopted shared-memory parallel programming model, is favored for its ease of use. However, it is still challenging to assist and accelerate automation of its parallelization. Although existing automation tools such as Cetus and DiscoPoP to simplify the parallelization, there are still limitations when dealing with complex data dependencies and control flows. Inspired by the success of deep learning in the field of Natural Language processing (NLP), this study adopts a Transformer-based model to tackle the problems of automatic parallelization of OpenMP instructions. We propose a novel Transformer-based multimodal model, ParaMP, to improve the accuracy of OpenMP instruction classification. the ParaMP model not only takes into account the sequential features of the code text, but also incorporates the code structural features and enriches the input features of the model by representing the Abstract Syntax Trees (ASTs) corresponding to the codes in the form of binary trees. In addition, we built a BTCode dataset, which contains a large number of C/C++ code snippets and their corresponding simplified AST representations, to provide a basis for model training. Experimental evaluation shows that our model outperforms other existing automated tools and models in key performance metrics such as F1 score and recall. this study shows a significant improvement on the accuracy of OpenMP instruction classification by combining sequential and structural features of code text, which will provide a valuable insight into deep learning techniques to programming tasks.

关键词： Deep learning Training Codes Automation Accuracy parallel programming Multicore processing

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MICRoFuzz: An Efficient Fuzzing Framework for Microservices

MICRoFuzz: An Efficient Fuzzing Framework for Microservices

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IEEE/ACM international conference on Software Engineering: Software Engineering in Practice Track (ICSE-SEIP)

作者： Peng Di Bingchang Liu Yiyi Gao Ant Group Hangzhou China Ant Group Beijing China

ISBN: (数字)9798400705014

ISBN: (纸本)9798350352177

Fuzzing is a widely adopted technique in the software industry to enhance security and software quality. However, most existing fuzzers are specifically designed for monolithic software architectures and face significant limitations when it comes to serving distributed Microservices applications (Apps). these limitations primarily revolve around issues of inconsistency, communication, and applicability which arise due to the differences in monolithic and distributed software architecture. this paper presents a novel fuzzing framework, called MICRO-Fuzz, specifically designed for Microservices. Mocking-Assisted Seed Execution, Distributed Tracing, Seed Refresh and Pipeline parallelism approaches are adopted to address the environmental complex-ities and dynamics of Microservices and improve the efficiency of fuzzing. MICROFuzz has been successfully implemented and deployed in Antgroup 1 , a prominent FinTech company. Its per-formance has been evaluated in three distinct industrial scenarios: normalized fuzzing, iteration testing, and taint verification. throughout five months of operation, MICROFuzz has diligently analyzed a substantial codebase, consisting of 261 Apps with over 74.6 million lines of code (LOC). the framework's effectiveness is evident in its detection of 5,718 potential quality or security risks, with 1,764 of them confirmed and fixed as actual security threats by software specialists. Moreover, MICROFuzz significantly increased line coverage by 12.24% and detected new paths by 38.42% in the iteration testing.

关键词： Industries Software architecture Pipelines Microservice architectures Software quality Fuzzing parallel processing

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Parameter prediction for unseen deep architectures 21

Parameter prediction for unseen deep architectures

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Proceedings of the 35th international conference on Neural Information processing Systems

作者： Boris Knyazev Michal Drozdzal Graham W. Taylor Adriana Romero-Soriano University of Guelph and Vector Institute for Artificial Intelligence Facebook AI Research University of Guelph and Vector Institute for Artificial Intelligence and Canada CIFAR AI Chair Facebook AI Research and McGill University

ISBN: (纸本)9781713845393

Deep learning has been successful in automating the design of features in machine learning pipelines. However, the algorithms optimizing neural network parameters remain largely hand-designed and computationally inefficient. We study if we can use deep learning to directly predict these parameters by exploiting the past knowledge of training other networks. We introduce a large-scale dataset of diverse computational graphs of neural architectures – DEEPNETS-1M– and use it to explore parameter prediction on CIFAR-10 and ImageNet. By leveraging advances in graph neural networks, we propose a hypernetwork that can predict performant parameters in a single forward pass taking a fraction of a second, even on a CPU. the proposed model achieves surprisingly good performance on unseen and diverse networks. For example, it is able to predict all 24 million parameters of a ResNet-50 achieving a 60% accuracy on CIFAR-10. On ImageNet, top-5 accuracy of some of our networks approaches 50%. Our task along with the model and results can potentially lead to a new, more computationally efficient paradigm of training networks. Our model also learns a strong representation of neural architectures enabling their analysis.

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