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parallel processing of Multi-dimensional Matrix Multiplication for Dynamic Dataset 5

Parallel Processing of Multi-dimensional Matrix Multiplicati...

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5th international conference on Electrical Information and Communication Technology, EICT 2021

作者： Shariar, Sarjil Hossain, Md. Safayet Azharul Hasan, K.M. Dept. of Computer Science and Engineering Khulna Bangladesh

ISBN: (纸本)9781665409063

Scientific and engineering computing demands multi-dimensional data processing in various domains including big data, machine learning, graph processing, object recognition, etc. In this paper, we process the multi-dimensional data model, also called high order tensor, with parallel computation on Graphics processing Unit (GPU). We introduce a dimension conversion technique to construct the Converted Matrix Structure (CMS) that transforms the n-dimensional tensor data into 2-dimensional matrix data with the dynamic memory allocation. With this scheme, we can extend the dimension size during runtime for the further inclusion of tensor elements. therefore the proposed scheme can handle the dynamic dataset that can expand during runtime. We also propose the parallel processing of matrix multiplication with the CMS scheme for improved and faster performance. To conduct the parallel processing of the multi-dimensional matrix multiplication (MDMMP), we first distribute the n-dimensional tensor elements on GPU threads to retrieve the 2-dimensional matrices, and then we process the Row-By-Column (RBC) wise multiplications of the matrices simultaneously. We perform these parallel processing in such a way that the load balance is ensured by the dynamic use of parallel threads based on the multi-dimensional data size. We found good speed up using our algorithm. © 2021 IEEE.

关键词： Tensors

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

30th International Conference on Parallel and Distributed Pr...

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

ISBN: (纸本)9783031856372

the proceedings contain 24 papers. the special focus in this conference is on parallel and Distributed processing Techniques. the topics include: parallel N-Body Performance Comparison: Julia, Rust, and More;REFT: Resource-Efficient Federated Training Framework for Heterogeneous and Resource-Constrained Environments;An Efficient Data Provenance Collection Framework for HPC I/O Workloads;using Minicasts for Efficient Asynchronous Causal Unicast and Byzantine Tolerance;a Comparative Study of Two Matrix Multiplication algorithms Under Current Hardware architectures;Is Manual Code Optimization Still Required to Mitigate GPU thread Divergence? Applying a Flattening Technique to Observe Performance;towards Automatic, Predictable and High-Performance parallel Code Generation;Attack Graph Generation on HPC Clusters;analyzing the Influence of File Formats on I/O Patterns in Deep Learning;inference of Cell–Cell Interactions through Spatial Transcriptomics Data Using Graph Convolutional Neural Networks;natural Product-Like Compound Generation with Chemical Language Models;improved Early–Modern Japanese Printed Character Recognition Rate with Generated Characters;Improved Method for Similar Music Recommendation Using Spotify API;Reconfigurable Virtual Accelerator (ReVA) for Large-Scale Acceleration Circuits;Building Simulation Environment of Reconfigurable Virtual Accelerator (ReVA);vector Register Sharing Mechanism for High Performance Hardware Acceleration;Efficient Compute Resource Sharing of RISC-V Packed-SIMD Using Simultaneous Multi-threading;introducing Competitive Mechanism to Differential Evolution for Numerical Optimization;hyper-heuristic Differential Evolution with Novel Boundary Repair for Numerical Optimization;jump Like a Frog: Optimization of Renewable Energy Prediction in Smart Gird Based on Ultra Long Term Network;vision Transformer-Based Meta Loss Landscape Exploration with Actor-Critic Method;Fast Computation Method for Stopping Condition of Range Restricted

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A Configurable Detector Based on Layered Belief Propagation for Massive MIMO Detection

A Configurable Detector Based on Layered Belief Propagation ...

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international conference on Integrated Circuits and Microsystems (ICICM)

作者： Rui Gao Houren Ji Wenyue Zhou Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS) National Mobile Communications Research Laboratory Southeast University Nanjing China Purple Mountain Laboratories Nanjing China

Massive multiple-input multiple-output (MIMO) detection plays a prominent role in the field of wireless communication. And with this trend, message passing detection (MPD) attracts a great attention since its advantages of high throughput and low complexity between distinct detection algorithms. Among various MPD algorithms, Gaussian approximate interference belief propagation (GAI-BP) detection can exhibit excellent convergence and performance in the different scenarios. However, its hardware design should be more efficient and flexible further. this paper proposes a novel semi-parallel hardware architecture for GAI-BP detection, aimed at improving its configurability using a layer scheduling scheme. through this scheme, the proposed detector achieves a gain of 0.65 dB when compared to the original algorithm, while simultaneously accommodating multi-antenna radios through the proposed hardware design.

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NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP Models 30

NLP-Fast: A Fast, Scalable, and Flexible System to Accelerat...

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30th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Kim, Joonsung Hur, Suyeon Lee, Eunbok Lee, Seungho Kim, Jangwoo Seoul Natl Univ Dept Elect & Comp Engn Seoul South Korea

ISBN: (纸本)9781665442787

Emerging natural language processing (NLP) models have become more complex and bigger to provide more sophisticated NLP services. Accordingly, there is also a strong demand for scalable and flexible computer infrastructure to support these large-scale, complex, and diverse NLP models. However, existing proposals cannot provide enough scalability and flexibility as they neither identify nor optimize a wide spectrum of performance-critical operations appearing in recent NLP models and only focus on optimizing specific operations. In this paper, we propose NLP-Fast, a novel system solution to accelerate a wide spectrum of large-scale NLP models. NLP-Fast mainly consists of two parts: (1) NLP-Perf : an in-depth performance analysis tool to identify critical operations in emerging NLP models and (2) NLP-Opt: three end-to-end optimization techniques to accelerate the identified performance-critical operations on various hardware platforms (e.g., CPU, GPU, FPGA). In this way, NLP-Fast can accelerate various types of NLP models on different hardware platforms by identifying their critical operations through NLP-Perf and applying the NLP-Opt's holistic optimizations. We evaluate NLP-Fast on CPU, GPU, and FPGA, and the overall throughputs are increased by up to 2.92x, 1.59x, and 4.47x over each platform's baseline. We release NLP-Fast to the community so that users are easily able to conduct the NLP-Fast's analysis and apply NLP-Fast's optimizations for their own NLP applications.

关键词： Architecture Computation/Dataflow Optimization Natural Language processing (NLP) parallel Algorithm

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A Proposed PWM Technique to Reduce Circulating Current in Two parallel Interleaved Two-Level VSIs

A Proposed PWM Technique to Reduce Circulating Current in Tw...

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India Council international Subsections conference (INDISCON), IEEE

作者： Monalika Kapil Shukla Harpal Tiwari Department of Electrical Engineering MNIT Jaipur

ISBN: (数字)9798350376753

ISBN: (纸本)9798350376760

By connecting inverters in parallel, a grid-connected converter system’s power processing capability can be improved. It has benefits including efficiency, dependability, and adaptability. However, there exists an instantaneous voltage mismatch between the inverter. this voltage mismatch may arise due to following situations: (i) phase shifting the carriers of the two inverters for interleaved pulse width modulation; (ii) running both VSIs at different power levels; and (iii) hardware problems such as dead time discrepancies, component limitations, etc. this instantaneous voltage difference produces a circulating current between the inverters. As a result, the efficiency of the overall system reduces. this paper proposes a carrier-based pulse width modulation approach to decrease circulating current in parallel connected 3- $\phi$ VSIs (equal distribution of power) running with interleaved PWM. To validate the PWM technique suggested, simulation data as well as a mathematical model are provided.

关键词： Voltage Pulse width modulation Inverters Vectors Mathematical models Hardware Proposals

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A Heterogeneous KBA parallel Algorithm for the Cartesian Discrete Ordinates for Multizone Heterogeneous System

A Heterogeneous KBA Parallel Algorithm for the Cartesian Dis...

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international conference on Computers, Communications, and Systems (ICCCS)

作者： Runhua Li Jie Liu Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

Innovations in powerful high-performance computing (HPC) architecture are enabling high-fidelity whole-core neutron transport simulations at reasonable time. Especially, the currently fashionable heterogeneous architectures make the cost of such simulations at very low level. Neutron distribution of a reactor core is governed by the Boltzmann neutron transport equation (BTE), first viable solutions of which need tremendous computer resources. Among of the high-fidelity numerical methods, the discrete ordinates method (SN) is becoming popular in the reaction design community by taking a good balance between computational cost and accuracy. Recently, MT-3000, which is a multizone heterogeneous architecture with a peak double precision performance of 11.6 TFLOPS, is proposed. In this work, the BTE is solved by the SN with heterogenous Koch-Baker-Alcouffe (KBA) parallel algorithms based on the MT-3000 architecture. A communication mechanism has been established to efficiently transmit data among the acceleration cores and the CPU cores. the kernel computation procedure is largely accelerated by the vectorization and instruction pipelining techniques. Numerical experiments show that our formulation could achieve 1.37 TFLOPs with single MT-3000, that is 11.8% of its peak performance.

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A Novel Steady and Redundant Frames Removal Performance Analysis of Video Background Subtraction algorithms with YOLOx Models

A Novel Steady and Redundant Frames Removal Performance Anal...

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Mobile Networks and Wireless Communications (ICMNWC), IEEE international conference on

作者： Sonali Karale Jatinderkumar R. Saini School of Computer Science and IT Jain (Deemed-to-be University) Bangalore India Symbiosis Institute of Computer Studies and Research Symbiosis International (Deemed University) Pune India

ISBN: (数字)9798331528348

ISBN: (纸本)9798331528355

One of the prime research areas today is video summarisation, where the short summary of the input video is generated. the output video content is based on the object of interest. It also saves the time of the viewer; they won't need to view the entire long duration video. To do this process faster, the redundant or steady frames need to be removed first. Background subtraction is one of the techniques used to identify moving objects by calculating the difference between previous and current frame. In our research paper, we have used KNN, MOG2 and CNT for the BGS methods. We have also used different YOLO model like YOLOv3, YOLOv5, YOLOv7 and YOLOv8 to generate annotations file and use them for measuring the performance of the BS algorithms. these methods are implemented using parallel processing approach to process more than one video at a time. the performance analysis of these methods is done based on the time of execution and precision. the experiment result shows that the KNN with YOLOv7 perform better and parallel processing approach speedup the execution.

关键词： YOLO Wireless communication Analytical models Instruction sets Nearest neighbor methods parallel processing Time measurement Libraries Performance analysis Object recognition

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parallel solvers comparison for an inverse problem in fractional calculus 14

Parallel solvers comparison for an inverse problem in fracti...

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14th IADIS international conference Computer Graphics, Visualization, Computer Vision and Image processing 2020, CGVCVIP 2020 and 5th IADIS international conference Big Data Analytics, Data Mining and Computational Intelligence 2020, BigDaCI 2020 and 9th IADIS international conference theory and Practice in Modern Computing 2020, TPMC 2020, Part of the 14th Multi conference on Computer Science and Information Systems, MCCSIS 2020

作者： De Luca, Pasquale Galletti, Ardelio Marcellino, Livia Department of Computer Science University of Salerno Fisciano Italy Department of Science and Technology University of Naples Parthenope Napoli Italy

ISBN: (纸本)9789898704214

High-Performance Computing (HPC) is a fundamental tool for improving the performance of many algorithms in terms of time, especially for large-scale problems. In the last years, various HPC architectures have been developed to quickly process data in many research areas and at the same time the HPC tools has become very important. In addition, the development of scientific libraries for parallel computing plays a key role in achieving better performance. In particular, thanks to the computational power of Graphic processing Units, themost popular and inexpensive accelerators, the parallel computing field has become almost a standard process for datamanagement. Hence, the porting of many standard numerical libraries on these architectures produced excellent results. In this work, we deal with a two-dimensional time fractional diffusion problem. More in detail, we analyze the performance of some parallel codes, specifically designed to solve it, implemented in different architectures. Moreover, a further GPU version is proposed and compared with the above implementations. © Proceedings of the 14th IADIS international conference Computer Graphics, Visualization, Computer Vision and Image processing 2020, CGVCVIP 2020 and Proceedings of the 5th IADIS international conference Big Data Analytics, Data Mining and Computational Intelligence 2020, BigDaCI 2020 and Proceedings of the 9th IADIS international conference theory and Practice in Modern Computing 2020, TPMC 2020 - Part of the 14th Multi conference on Computer Science and Information Systems, MCCSIS 2020. All rights reserved.

关键词： Graphics processing unit

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5G Channel Estimation Kernels on RISC-V Vector Digital Signal Processors

5G Channel Estimation Kernels on RISC-V Vector Digital Signa...

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international conference on Microelectronics, ICM

作者： Javier Acevedo Frank H. P. Fitzek Patrick Seeling Deutsche Telekom Chair of Communication Networks Dresden TU Centre for Tactile Internet with Human-in-the-Loop (CeTI) Department of Computer Science Central Michigan University

ISBN: (数字)9798350379396

ISBN: (纸本)9798350379402

Each generation of the wireless communication networks has contiguous demands for higher computing capabilities and lower the power consumption in the integrated circuitry. thus, the optimization of the base-band signal processing kernels and the hardware architectures plays a pivotal role in the performance, latency, and energy efficiency of the Physical Layer (PHY). Channel Estimation (CE), a computationally intensive task with hard real-time requirements, involves significant amounts of matrix multiplications and inversions, when data flows between transmitter (TX) and receiver (RX). In this work, we present a software implementation of CE for the 5th Generation Cellular Networks (5G) New Radio (NR) in the Reduced Instruction Set Computer (RISC)-V architecture, showcasing how its vector processing capabilities can satisfy the throughput and delay requirements of 5G use cases. Specifically, we ported two CE kernels, the Least-Squares (LSE) and Minimum Mean Square Error (MMSE), onto a state-of-the-art single core vector processor. By exploiting data vectorization, the ARA core computes matrix arithmetic operations on multiple data sets simultaneously. Our single vector core serial optimization demonstrates that with a $16\times 16$ matrix window size and 16 vector lanes, the application's performance achieves a speedup of 78.27 when computing the LSE algorithm. When the number of operations per cycle are compared, the vector processor outperforms its scalar counterpart by 181.91 for the MMSE kernel. Our implementation orders the nested loops in a latency-reducing fashion to compute matrix arithmetic operations, resulting in LSE and MMSE estimator computing times of $8.44 \mu\iota \mathrm{s}$ and $12.31\ \mu\mathrm{s}$ , respectively.

关键词： Channel estimation Signal processing algorithms Computer architecture Vectors Hardware Vector processors Matrix decomposition Kernel Optimization Clocks

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High-throughput VLSI architectures for VLSI Signal processing 5th

High-Throughput VLSI Architectures for VLSI Signal Processin...

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5th international conference on Microelectronics, Electromagnetics and Telecommunication, ICMEET 2019

作者： Varma, R. Ashok Chaitanya Subbarao, M. Venkata Varma, D. Ramesh Raju, G.R.L.V.N.S. Bhimavaram India

ISBN: (纸本)9789811538278

the purpose of this work is to develop VLSI DSP architectures for CRC-32 generator polynomial equation to improve better throughput with less number of clock pulses. In this paper, IIR filter-based design method is proposed. Different levels of architectures are proposed to achieve the requirement. LFSR is used in developing VLSI DSP architectures. these architectures had been implemented in Xilinx tool. © 2020, Springer Nature Singapore Pte Ltd.

关键词： IIR filters

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