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16th international Euro-Par conference on parallel processing

作者： Amestoy, Patrick di Serafino, Daniela Bisseling, Rob Quintana-Orti, Enrique S. Vajtersic, Marian Univ Toulouse Toulouse France Univ Naples 2 Naples Italy CNR ICAR Naples Italy Univ Utrecht Utrecht Netherlands Univ Jaime I Castellon de La Plana Spain Salzburg Univ A-5020 Salzburg Austria

ISBN: (纸本)9783642152900

Robust and efficient parallel numerical algorithms and their implementation in easy-to-use portable software components are crucial for computational science and engineering applications. they are strongly influenced by the remarkable progress in the development of parallel computer systems. this imposes to adapt or re-design already existing algorithms, or to find new algorithmic approaches, in order to effectively exploit the power that is offered by emerging parallel architectures. On the other hand, the use of numerical algorithms and software in more and more complex applications, to make simulations and computational experiments with a very high level of detail, demands for increasing computing power, thus giving new stimulating impulses to parallel computer developers. the aim of Topic 10 is to provide a forum for the presentation and discussion of recent advances in the field of parallel and distributed numerical algorithms. Different aspects of their design and implementation are addressed, ranging from fundamental algorithmic concepts, through their efficient implementation on modern parallel architectures, up to software design and prototyping in scientific computing and simulation software environments, and to performance analysis. © 2010, Springer-Verlag Berlin Heidelberg.

关键词： parallel architectures

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An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. this is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. this hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

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A Customized processing-in-Memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. the design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

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A parallel Algorithm of Kirchhoff Pre-stack Depth Migration Based on GPU 1

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14th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Wang, Yida Li, Chao Tian, Yang Yan, Haihua Zhao, Changhai Zhang, Jianlei Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China

ISBN: (数字)9783319111940

ISBN: (纸本)9783319111940;9783319111933

Kirchhoff pre-stack depth migration (KPSDM) algorithm, as one of the most widely used migration algorithms, plays an important part in getting the real image of the earth. However, this program takes considerable time due to its high computational cost;hence the working efficiency of the oil industry is affected. the general purpose Graphic processing Unit (GPU) and the Compute Unified Device Architecture (CUDA) developed by NVIDIA have provided a new solution to this problem. In this study, we have proposed a parallel algorithm of the Kirchhoff pre-stack depth migration and an optimization strategy based on the CUDA technology. Our experiments indicate that for large data computations, the accelerated algorithm achieves a speedup of 8 similar to 15 times compared with NVIDIA GPU.

关键词： Kirchhoff pre-stack depth migration GPU CUDA parallel algorithm optimization

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Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders

Formal Proof for a General Architecture of Hybrid Prefix/Car...

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10th international conference on algorithms and architectures for parallel processing

作者： Liu, Feng Tan, Qingping Song, Xiaoyu Chen, Gang National Lab. of Parallel Distributed Processing Hunan China ECE Department Portland State University Portland OR United States Lingcore Lab. Portland OR United States

ISBN: (纸本)9783642131189

In this paper, we present a general architecture of hybrid prefix/carry-select adder. Based on this architecture, we formalize the hybrid adder's algorithm using the first-order recursive equations and develop a proof framework to prove its correctness. Since several previous adders in the literature are special cases of this general architecture, our methodology can be used to prove the correctness of different hybrid prefix/carry-select adders. the formal proof for a special hybrid prefix/carry-select adder shows the effectiveness of the algebraic structures built in this paper.

关键词： Adders

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Generalized Approach to Scalability Analysis of parallel Applications 16th

Generalized Approach to Scalability Analysis of Parallel App...

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16th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Antonov, Alexander Teplov, Alexey Moscow MV Lomonosov State Univ Moscow Russia

ISBN: (纸本)9783319499567;9783319499550

this article describes an approach to scalability analysis of parallel applications, which is a major part of the algorithm description used in AlgoWiki, the Open Encyclopedia of parallel Algorithmic Features. the proposed approach is based on the suggested definition of generalized scalability of a parallel application. this study uses joined and structured data on an application's execution and supercomputing co-design technologies. parallel application properties are studied by analyzing data collected from all available sources of its dynamic characteristics and information about the hardware and software platforms corresponding with the features of an algorithm and its implementation. this allows reasonable conclusion to be drawn regarding potential reasons of changes in the execution quality for any parallel applications and to compare the scalability of various programs.

关键词： Scalability Dynamic characteristics Efficiency parallel computing Supercomputing co-design

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Exploitation of control parallelism in data parallel algorithms

Exploitation of control parallelism in data parallel algorit...

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Proceedings of the 5th Symposium on the Frontiers of Massively parallel Computation

作者： Garg, Vivek Schimmel, David E. Georgia Inst of Technology Atlanta United States

this paper considers the matrix decomposition A = LDLT, as a vehicle to explore the improvement in performance obtainable through the execution of multiple streams of control on SIMD architectures. Several methods for partitioning the SIMD array are considered. Architectural support for and feasibility of using control parallelism in SIMD algorithms is briefly considered. Techniques for converting the extracted control parallelism into increased performance are illustrated via their application to the example algorithm. Analytical expressions for execution times are expressed in terms of execution times of the constituent operations. Experimental results for the various partitioning schemes based on execution traces are also presented. Timings based on Mas-Par MP-2 operations and extrapolated from experimental data are used to compare the various control parallel versions of the algorithm and the traditional SIMD counterpart.

关键词： parallel processing systems

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Scheduling independent tasks on multi-cores with GPU accelerators

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2015年第6期27卷 1625-1638页

作者： Bleuse, Raphael Kedad-Sidhoum, Safia Monna, Florence Mounie, Gregory Trystram, Denis Univ Paris 06 Sorbonne Univ UMR 7606 LIP6 F-75005 Paris France Univ Grenoble Alpes LIG F-38334 Saint Ismier France Inst Univ France Paris France

More and more computers use hybrid architectures combining multi-core processors and hardware accelerators such as graphics processing units (GPUs). We present in this paper a new method for scheduling efficiently parallel applications with m CPUs and k GPUs, where each task of the application can be processed either on a core (CPU) or on a GPU. the objective is to minimize the maximum completion time (makespan). the corresponding scheduling problem is Non-deterministic Polynomial (NP)-time hard, Copyright (c) 2014 John Wiley & Sons, Ltd.

关键词： scheduling approximation algorithms parallel heterogeneous systems

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Emotional Contribution Process Implementations on parallel Processors

Emotional Contribution Process Implementations on Parallel P...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Dominguez, Carlos Hassan, Houcine Albaladejo, Jose Marco, Maria Crespo, Alfons Univ Politecn Valencia Dept Informat Sistemas & Comp E-46071 Valencia Spain

ISBN: (纸本)9783642246685

An emotional agent software architecture for real-time mobile robotic applications has been developed. In order to allow the agent to undertake more dynamically constrained application problem solving, the processor computation time should be reduced and the gained time is used for executing more complex processes. In this paper, the response time of the operating processes, in each attention cycle of the agent, is decreased by parallelizing the highly parallel processes of the architecture, namely, emotional contribution processes. the implementation of these processes has been evaluated in Field Programmable Gate Array (FPGA) and multicore processors.

关键词： FPGA Multicore Load balancing Robotics Agents Real-time

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A skeleton for parallel dynamic programming

A skeleton for parallel dynamic programming

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5th international Euro-Par conference

作者： Morales, D Almeida, F Garcia, F Gonzalez, J Roda, J Rodriguez, C Univ La Laguna Dpto EIO & Computac Ctr Super Informat Tenerife Spain

ISBN: (纸本)3540664432

the development of skeleton tools constitutes an alternative to cover the gap between current parallel architectures and sequential programmers. Its contruction involves formal models, paradigms and methologies. Based in the automata theory we have developed a formal model for parallel Dynamic Programming over pipeline networks. this model makes up a paradigm which is the core of skeleton tools oriented to the Dynamic Programming Technique. Following the methodology coerced by the model, we present a tool that provides the user with the ability to obtain parallel programs adapted to the parallel architecture. the efficiency is contrasted on three current parallel platforms: Gray T3E, IBM SP2 and SG Origin 2000.

关键词： parallel architectures

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