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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3284 条记录，以下是381-390 订阅

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Skywalker: Efficient Alias-method-based Graph Sampling and Random Walk on GPUs 30

Skywalker: Efficient Alias-method-based Graph Sampling and R...

引用

30th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Wang, Pengyu Li, Chao Wang, Jing Wang, Taolei Zhang, Lu Leng, Jingwen Chen, Quan Guo, Minyi Shanghai Jiao Tong Univ Dept Comp Sci & Engn Shanghai Peoples R China Shanghai Qi Zhi Inst Shanghai Peoples R China

ISBN: (纸本)9781665442787

Graph sampling and random walk operations, capturing the structural properties of graphs, are playing an important role today as we cannot directly adopt computing-intensive algorithms on large-scale graphs. Existing system frameworks for these tasks are not only spatially and temporally inefficient, but many also lead to biased results. this paper presents Skywalker, a high-throughput, quality-preserving random walk and sampling framework based on GPUs. Skywalker makes three key contributions: first, it takes the first step to realize efficient biased sampling with the alias method on a GPU. Second, it introduces well-crafted load-balancing techniques to effectively utilize the massive parallelism of GPUs. third, it accelerates alias table construction and reduce the GPU memory requirement with efficient memory management scheme. We show that Skywalker greatly outperforms the state-of-the-art CPU-based and GPU-based baselines, in a wide spectrum of workload scenarios.

关键词： Graph sampling random walk graphics processing unit

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PAMIHR. A parallel FORTRAN program for multidimensional quadrature on distributed memory architectures

PAMIHR. A parallel FORTRAN program for multidimensional quad...

引用

5th international Euro-Par conference

作者： Laccetti, G Lapegna, M Univ Naples Federico II CNR Ctr Res Parallel Comp & Supercomp I-80126 Naples Italy

ISBN: (纸本)3540664432

PAMIHR: a parallel adaptive routine for the approximate computation of a multidimensional integral over a hyperrectangular region is described. the software is designed to efficiently run on a MIMD distributed memory environment, and it's based on the widely diffused communication system BLACS. PAMIHR, further, gives special attention to the problems of scalability and of load balancing among the processes.

关键词： Memory architecture

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A non-blocking multithreaded architecture with support for speculative threads

A non-blocking multithreaded architecture with support for s...

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8th international conference on algorithms and architectures for parallel processing

作者： Kavi, Krishna Li, Wentong Hurson, Ali Univ North Texas Denton TX 76203 USA Missouri Univ Sci & Technol Rolla MO USA

ISBN: (纸本)9783540695004

In this paper we provide both a qualitative and a quantitative evaluation of a decoupled multithreaded architecture that uses non-blocking threads. Our architecture is based on simple in-order pipelines and complete decoupling of memory accesses from execution pipelines. We extend the architecture to support thread level speculation using snooping cache coherency protocols. We evaluate the performance gains from speculations by varying the number of load/store instructions compared to computational instructions, miss speculation rates and the degree of thread level speculation. Our architecture presents a viable alternative to complex superscalar and super-speculative CPUs.

关键词： multithreaded architectures cache coherency thread level speculation decoupled architecture

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Implementing a space-aware stochastic simulator on low-power architectures: a systems biology case study 25

Implementing a space-aware stochastic simulator on low-power...

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25th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Morganti, Lucia Corni, Elena Ferraro, Andrea Cesini, Daniele D'Agostino, Daniele Merelli, Ivan Italian Inst Nucl Phys CNAF Bologna Italy Natl Res Council Italy Inst Appl Math & Informat Technol E Magenes Genoa Italy Natl Res Council Italy Inst Biomed Technol Segrate Mi Italy

ISBN: (纸本)9781509060580

In the last decade, different computing paradigms and modelling frameworks for the description and simulation of biochemical systems based on stochastic modelling have been proposed. From a computational point of view, many simulations of the model are necessary to identify the behaviour of the system. the execution of thousands of simulations can require huge amount of time, therefore the parallelization of these algorithms is highly desirable. In particular, models that consider the size of volumes and objects involved in the reaction are very time-consuming, since many rules should be considered to take into account the position of the different molecules. In this work we present an implementation of a stochastic space-aware simulator which exploits the benefit and features of hybrid low-power computing architectures. this work shows that the simulator dynamic probabilistic approach to select possible chemical reactions can be applied and implemented in hybrid low-power low-cost architectures as well as current industry high-end servers.

关键词： Computational modeling Biological system modeling Stochastic processes Computer architecture Evolution (biology) Biomembranes Power system dynamics

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Exploiting image processing locality in cache pre-fetching 5

Exploiting image processing locality in cache pre-fetching

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5th international conference on High Performance Computing

作者： Cucchiara, R Piccardi, M Univ Ferrara Dipartimento Ingn I-44100 Ferrara Italy

ISBN: (纸本)0818691948

Emerging trends in computer design attempt to include specific solutions for handling images also in general-purpose computers, because of the current spread of multimedia, image processing and computer graphics applications. In this context, this paper proposes hardware pre-fetching techniques specific for caching images: the main issue we state is that most algorithms working opt images exhibit a 2D spatial locality that is not taken into account in current cache organization and data access strategies. To this aim we propose an adaptive local pre-fetching for the image data type;this technique, mirroring the two-dimensional spatial locality of image processing algorithms, results to be more efficient than other approaches, such as sequential pre-fetching and adaptive pre-fetching. Performance is evaluated on different classes of image processing algorithms, namely raster-scan and propagative algorithms, common in computer vision and multimedia applications.

关键词： General purpose computers

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A parallel Solution of Large-Scale Heat Equation Based on Distributed Memory Hierarchy System

A Parallel Solution of Large-Scale Heat Equation Based on Di...

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10th international conference on algorithms and architectures for parallel processing

作者： Cheng, Tangpei Wang, Qun Ji, Xiaohui Li, Dandan China Univ Geosci Beijing Sch Informat Engn Beijing 100083 Peoples R China

ISBN: (纸本)9783642131356

A parallel scheme for distributed memory hierarchy system is presented to solve the large-scale three-dimensional heat equation. Since managing interprocess communications and coordination is the main difficulty with the system, the local physics/global algebraic object paradigm is introduced. Domain decomposition method is used to partition the modeling area, as well as the intensive computational effort and large memory requirement. Efficient storage and assembly of sparse matrix and parallel iterative solution of linear system are considered and developed. the efficiency and scalability of the parallel program are demonstrated by completing two experiments on Linux cluster, in which different preconditioning methods are tested and analyzed. And the results demonstrate this method could achieve desirable parallel performance.

关键词： Domain decomposition methods

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Controlled Asynchronous GVT: Accelerating parallel Discrete Event Simulation on Many-Core Clusters 19

Controlled Asynchronous GVT: Accelerating Parallel Discrete ...

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48th international conference on parallel processing (ICPP)

作者： Eker, Ali Williams, Barry Chiu, Kenneth Ponomarev, Dmitry Binghamton Univ Binghamton NY 13902 USA

ISBN: (纸本)9781450362955

In this paper, we investigate the performance of parallel Discrete Event Simulation ( PDES) on a cluster of many-core Intel KNL processors. Specifically, we analyze the impact of different Global Virtual Time (GVT) algorithms in this environment and contribute three significant results. First, we show that it is essential to isolate the thread performing MPI communications from the task of processing simulation events, otherwise the simulation is significantly imbalanced and performs poorly. this applies to both synchronous and asynchronous GVT algorithms. Second, we demonstrate that synchronous GVT algorithm based on barrier synchronization is a better choice for communication-dominated models, while asynchronous GVT based on Mattern's algorithm performs better for computation-dominated scenarios. third, we propose Controlled Asynchronous GVT (CA-GVT) algorithm that selectively adds synchronization to Mattern-style GVT based on simulation conditions. We demonstrate that CA-GVT outperforms both barrier and Mattern's GVT and achieves about 8% performance improvement on mixed computation-communication models. this is a reasonable improvement for a simple modification to a GVT algorithm.

关键词： parallel Discrete Event Simulation Intel Xeon Phi Knights Landing Manycore architectures Performance Global Virtual Time

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Mathematical modelling of continuous optimal multilevel paralleling

Mathematical modelling of continuous optimal multilevel para...

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5th IASTED international conference on Modelling, Simulation and Optimization

作者： Riismaa, T Tallinn Univ Technol Inst Cybernet Akadeemia Tee 21 EE-12618 Tallinn Estonia

ISBN: (纸本)0889865248

A method of description and optimization of the continuous structure of hierarchical processing system is presented. the structure of the system is defined as a finite sequence of density functions of distributions. Each distribution will correspond to the connections between this and previous level and shows how the size of previous level is distributed between the sizes of this level. Corresponding optimization problem is a calculus of variations problem. Some reduced variants of this problem have good mathematical properties and is solved analytically. the approach is given in terms of convex analysis, integer programming and calculus of variations.

关键词： parallel and distributed architectures optimal multi-level partitioning

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Modular Resultant Algorithm for Graphics Processors

Modular Resultant Algorithm for Graphics Processors

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10th international conference on algorithms and architectures for parallel processing

作者： Emeliyanenko, Pavel Max Planck Inst Informat Saarbrucken Germany

ISBN: (纸本)9783642131189

In this paper we report on the recent progress in computing bivariate polynomial resultants on Graphics processing Units (GPU). Given two polynomials in Z[x, y], our algorithm first maps the polynomials to a prime field. then, each modular image is processed individually. the GPU evaluates the polynomials at a number of points and computes univariate modular resultants in parallel. the remaining "combine" stage of the algorithm is executed sequentially on the host machine. Porting this stage to the graphics hardware is an object of ongoing research. Our algorithm is based on an efficient modular arithmetic from [1]. With the theory of displacement structure we have been able to parallelize the resultant algorithm up to a very fine scale suitable for realization on the GPU. Our benchmarks show a substantial speed-up over a host-based resultant algorithm [2] from CGAL (***).

关键词： polynomial resultants modular algorithm parallel computations graphics hardware GPU CUDA

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A parallel LUMA-CHROMA FILTERING ARCHITECTURE FOR H.264/AVC DEBLOCKING FILTER 5

A PARALLEL LUMA-CHROMA FILTERING ARCHITECTURE FOR H.264/AVC ...

引用

5th IEEE international conference on Consumer Electronics Berlin

作者： Kefalas, Nikolaos theodoridis, George Univ Patras ECE Dept VLSI Design Lab Patras 26500 Greece

ISBN: (纸本)9781479987481

A novel architecture for the H.264/AVC deblocking filter is proposed. It includes three filtering units to filter in parallel the luma and chroma components. Also, a proper two dimensional filtering order for the luma edges and a one-dimensional filtering order for the chroma edges are presented. the architecture achieves 750 MHz in 560 MHz in 90nm and 130 nm, respectively, and requires 76 cycles to filter each MB. Compared to existing architectures, it outperforms them in frequency and throughput, while it is the only one that achieves over 60 Fps in 8K-UHD resolution.

关键词： H.264 Deblocking UHD Pipeline throughput

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