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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3293 条记录，以下是31-40 订阅

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Modified FIR Filter and High Speed Adder for Signal processing Applications 5

Modified FIR Filter and High Speed Adder for Signal Processi...

引用

5th international conference on IoT Based Control Networks and Intelligent Systems, ICICNIS 2024

作者： Sakthi, K. Karthikeyan, J. Jaya Surya, M. Saveetha Engineering College Department of Electronics and Communication Engineering Chennai India

ISBN: (数字)9798331518097

ISBN: (纸本)9798331518097

Low-power, high-performance digital signal processing is becoming more and more crucial. the most commonly used basic components of DSP systems are filters with finite impulse response. these complete filter topologies were created utilizing the Modified Carry Select Adder and Ripple Carry Adder in accordance with the parallel FIR digital filter's performance analysis. Since adders are less costly than multipliers in terms of silicon area, the switch is feasible. We will compare the performance of parallel FIR filter topologies based on Carry Select Adder and Ripple Carry Adder. © 2024 IEEE.

关键词： FIR filters

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Research on Performance Analysis Techniques for parallel Program Optimization on Domestic CPU Architecture 5

Research on Performance Analysis Techniques for Parallel Pro...

引用

5th international conference on Information Science, parallel and Distributed Systems, ISPDS 2024

作者： Zhu, Sheng Zhou, Cheng Li, Weiwei Luo, Fucai Ji, Wen State Grid Smart Grid Research Institue Co. Ltd Beijing China

ISBN: (纸本)9798350352719

With the increasing use of high-performance computing, users are turning to programs for concurrent execution enhance the speed and overall performance of large-scale programs. this trend is supported through the use of a portable messaging interface (MPI), communication can be facilitated in a convenient and efficient manner. We employ the MPI-based performance analysis tool mpiP for evaluating program performance, focusing on a matrix multiplication model through numerous targeted experiments with a fixed number of processors. Expanding the scale of the experimental use case matrix;fixing the scale of the matrix and scaling up the number of processors in order to clearly analyze the program performance and improve the performance analysis of mpiP. At the same time, the execution sequence detection and visualization functions are added in the improvement process. the mpiP report makes it easier for users to perform global performance analysis on the program. this not only improves the overall performance analysis efficiency, it also facilitates tracking the progress of individual processes throughout the program's execution. © 2024 IEEE.

关键词： parallel architectures

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Hardware Implementation of Image processing Morphological and Convolution Operations as SoC on FPGAs 24

Hardware Implementation of Image Processing Morphological an...

引用

7th international conference on Digital Medicine and Image processing, DMIP 2024

作者： Moussa, Alfred M. Groves, Richard Rafla, Nader Electrical and Computer Engineering Department Boise State University BoiseID United States

ISBN: (纸本)9798400709586

Efficient image processing architectures are consistently in demand across a multitude of applications, particularly those customized for resource-constrained systems-on-chip (SoC). the increasing need for high-performance image processing in various sectors has driven the development of specialized architectures. However, deploying such architectures on platforms with limited resources, such as SoCs, poses significant challenges. Furthermore, the implementation of complex algorithms to handle large datasets using software solutions often leads to slower response times, prompting exploration into hardware implementations. Field-Programmable Gate Arrays (FPGAs) are becoming popular for hardware implementations because of their attributes: low latency, connectivity, parallel computing capabilities, and flexibility. Consequently, the utilization of FPGA-based implementations has resulted in faster and more efficient performance of unique architectures tailored to specific requirements. this paper presents a novel hardware/software co-design approach to implement erosion, dilation, and neighborhood image processing operations on the FPGA development board, "Zedboard". In this approach, the FPGA is programmed by connecting it to a PC via USB, facilitating the transfer of an image pixel by pixel. the pixels are temporarily stored in on-chip DDR and accessed through DMA (Direct Memory Access) until they are requested by an interrupt signal from the Image processing IP, at which point they are moved to line buffers for faster processing. Once processed, the image is transmitted back to the PC via UART, facilitating pixel-by-pixel transfer for verification, where it is compared with a reference image generated using Python. this comparison confirms a 99.22% match between the processed image and the reference image, with the discrepancy occurring at the image's edges due to initial padding. Additionally, the time required to process the entire image was measured and displayed

关键词： System-on-chip

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Performance Comparison of Distributed DNN Training on Optical Versus Electrical Interconnect Systems 23rd

Performance Comparison of Distributed DNN Training on Optica...

引用

23rd international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Dai, Fei Chen, Yawen Huang, Zhiyi Zhang, Haibo Tian, Hui Univ Otago Sch Comp Dunedin New Zealand Eastern Inst Technol Pukenga Sch Comp Napier New Zealand Griffith Univ Sch Informat & Commun Technol Brisbane Qld Australia

ISBN: (纸本)9789819708338;9789819708345

parallel and distributed Deep Neural Network (DNN) training have become integral in data centers, significantly reducing DNN training time. the interconnection type among nodes and the chosen all-reduce algorithm critically impact this speed-up. this paper examines the efficiency differences in distributed DNN training across optical and electrical interconnect systems using various all-reduce algorithms. We first explore the Ring and Recursive Doubling (RD) all-reduce algorithms in both systems, followed by formulating a communication cost model for these algorithms. Performance comparison is then carried out via extensive experiments. Our results reveal that, in 1024-node systems, the Ring algorithm outperforms the RD algorithm in optical and electrical interconnects when data transfer exceeds 64MB and 1024 MB, respectively. We also find that both Ring and RD algorithms in optical interconnect systems reduce average communication time by around 75% compared to electrical interconnect systems across four different DNNs. Interestingly, the communication time of the RD algorithm, but not the Ring algorithm, reduces as the number of wavelengths increase in optical interconnects. these findings provide valuable insights into DNN training optimization across various interconnect systems and lay the groundwork for future related research.

关键词： Performance comparison Distributed DNN training Electrical interconnect Optical interconnect Performance comparison parallel computation

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Comparative Analysis of parallel and Cascaded architectures for the Realization of High-Speed FIR Filters with FPGA 5

Comparative Analysis of Parallel and Cascaded Architectures ...

引用

5th international conference on Inventive Research in Computing Applications, ICIRCA 2023

作者： Kumari, Apurva Mahidhar, Lolla Manideep, Kotha Mounika, Kodali B v Raju Institute of Technology Dept. of Ece Narsapur India

ISBN: (纸本)9798350321425

this research work presents a detailed analysis on the design and implementation of parallel and cascade topologies in addition to the realization of high-speed FIR filters using FPGAs. An FPGA-based FIR filter's design, implementation, and verification using Verilog HDL are thoroughly analyzed. It is demonstrated that the filter's hardware implementation is effective in terms of clock frequency, utilization of resources, and latency. the architectures are also contrasted, and their benefits and shortcomings are discussed. the parallel architecture is better suitable for high-speed FIR filters than the cascade architecture, according to implementation findings on a Xilinx Spartan-3E FPGA and a VIRTEX FPGA. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Research on the Application of Natural Language processing Technology in Medicine Patent Retrieval 5

Research on the Application of Natural Language Processing T...

引用

5th international conference on Information Science, parallel and Distributed Systems, ISPDS 2024

作者： Tu, Lan Lv, Shuojun Shi, Hui Shanwei Polytechnic Department of Information Engineering Shanwei516600 China Shanwei Innovation Industrial Design and Research Institute Research Institute of Cloud Computing and Data Center Project Design Shanwei516600 China

ISBN: (纸本)9798350352719

In view of the high professionalism and complexity of medicine patent text, traditional patent retrieval mainly relies on manual operation and simple text processing methods, this paper aims to use Natural Language processing (NLP) technology to efficiently obtain valuable information in medicine patent retrieval. To transform unstructured text into meaningful information. through in-depth research on the characteristics and structure of medicine patent text, a new structured feature extraction algorithm of patent text is proposed, and a patent retrieval system based on NLP is developed, which can carry out instant structured processing, and can automatically identify and translate text into corresponding patented medicines, and nearly 300 medicine patent abstracts are tested by experiment. the system performance is good. the system achieves the expected effect. © 2024 IEEE.

关键词： Patents and inventions

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Analysis and Comparison of Partial Power processing Converter architectures for EV Fast Charging Station 5

Analysis and Comparison of Partial Power Processing Converte...

引用

5th IEEE international Transportation Electrification conference, ITEC-India 2023

作者： Satapathy, Manoranjan Siddhartha, Vishwanatha Shivakumar, Gudelli Edpuganti, Amarendra Indian Institute of Technology Kanpur Department of Sustainable Energy Engineering Kanpur India

ISBN: (纸本)9798350337808

the main objective of this paper is to analyze and compare various partial power processing converter (PPPC) architectures for electric vehicle (EV) fast chargers. Detailed mathematical analyses of the possible PPPC architectures are presented. the comparison of these architectures is done in terms of converter input and output current and voltages, overall system efficiency, and partial power processed ratio. Based on this analysis, the best possible architecture for a 350 kW-rated EV fast charger is suggested with respect to the most suitable DC-link voltage. the simulation analysis is done in the MATLAB environment. © 2023 IEEE.

关键词： Charging (batteries)

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SuperCut: Communication-Aware Partitioning for Near-Memory Graph processing 23

SuperCut: Communication-Aware Partitioning for Near-Memory G...

引用

20th ACM international conference on Computing Frontiers (CF)

作者： Zhao, Chenfeng Chamberlain, Roger D. Zhang, Xuan Washington Univ McKelvey Sch Engn St Louis MO 63110 USA

ISBN: (纸本)9798400701405

the parallel execution of many graph algorithms is frequently dominated by data communication overheads between compute nodes. this bottleneck becomes even more pronounced in Near-Memory processing (NMP) architectures with multiple memory cubes as local memory accesses are less expensive. Existing near-memory architectures typically use graph partitioning methods with a fixed vertex assignment, which limits their potential to improve performance and reduce energy consumption. Here, we argue that an NMP-based graph processing system should also consider the distribution of vertices onto memory cubes. We propose SuperCut, a framework for near-memory architectures to effectively reduce communication overheads while maintaining computational balance. We evaluate SuperCut via architectural simulation with 6 real-world datasets and 4 representative applications. the results show that it provides up to 1.8x total energy reduction and 2.6x speedup relative to current state-of-the-art approaches.

关键词： near-data processing 3D-stacked memory graph processing

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GGPA: A General Graph processing Architecture with Flexible Execution Paradigm 23

GGPA: A General Graph Processing Architecture with Flexible ...

引用

20th ACM international conference on Computing Frontiers (CF)

作者： Zhang, Bin Du, Haitao Chen, Song Kang, Yi Univ Sci & Technol China Hefei Anhui Peoples R China

ISBN: (纸本)9798400701405

Currently, graph data are particularly common in various fields, and graph algorithms are increasingly widely used. However, due to the features of graph datasets, such as sparsity, the acceleration of graph algorithms with traditional architectures is faced with great challenges. In terms of domain-specific architecture (DSA), accelerators are mostly designed for a specific graph algorithm because of the different features of different graph algorithms. there is still a great need for a general graph algorithmic processing architecture. In this work, we propose a parallel General Graph processing Architecture, GGPA. As a general graph computing architecture, GGPA can support multiple graph algorithms, realize parallel processing and fully explore the parallelism through a unique and effective subgraph partitioning method. GGPA implements flexibility at the execution paradigm level. During algorithm iteration, GGPA dynamically selects the execution paradigm by analyzing vertex update conditions to achieve the best performance. We verify GGPA at the CPU level and architecture simulator level, and experimental results show that GGPA achieves 1.01x to 5.86x speedup compared to other related start-of-the-art work.

关键词： graph analytics parallel processing domain-specific architecture flexible execution paradigm

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Research on parallel Computing Method of Kalman Filter Based on CUDA 5

Research on Parallel Computing Method of Kalman Filter Based...

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5th international conference on Artificial Intelligence and Electromechanical Automation, AIEA 2024

作者： Sheng, Panlong He, Pengju Xu, Yimei Zhao, Xiangmei Xi'an Eurasia University School of Information Engineering Xi'an China

ISBN: (纸本)9798350366174

the Kalman filter is an important tool for state estimation of linear dynamic systems and is widely used in signal processing, control systems, navigation and other fields. the computational efficiency of the traditional Kalman filter is limited when processing large-scale data. this article proposes a Kalman filter parallel computing method based on CUDA (Compute Unified Device Architecture), which improves processing speed by executing filter steps in parallel on the GPU. Experimental results show that compared with traditional CPU implementation, the Kalman filter implemented by CUDA shows significant acceleration effect on large data sets. © 2024 IEEE.

关键词： Kalman filters

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