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Research on CUDA-based Multidimensional Time Series Motif Mining

Research on CUDA-based Multidimensional Time Series Motif Mi...

引用

Computer, Big Data and Artificial Intelligence (ICCBD+AI), international conference on

作者： Jimin Wang Shuaiwei Wang Junru Wang College of Computer Science and Software Engineering Hohai University Nanjing China

ISBN: (数字)9798331533991

ISBN: (纸本)9798331534004

Traditional serial motif mining methods struggle to quickly identify motif information in large-scale time series data. A CUDA-based multidimensional motif mining algorithm is proposed to discover motifs in multidimensional time series. the algorithm introduces a multidimensional kNN Matrix Profile (kNN mMP) structure to address the limitations of the multidimensional mMP. parallel computation of kNN mMP using the CUDA architecture enables rapid motif discovery in massive datasets and facilitates detection of additional motif features, such as strong and weak motifs, as well as identification of anomalous motifs. Experiments on public datasets demonstrate that using CUDA for kNN mMP structure achieves a significant speedup; on NVIDIA GeForce RTX 4060, the kNN-mSTOMP-GPU algorithm exhibits a speedup of over 220 times compared to the STOMP algorithm utilizing only kNN mMP when the sequence length is 200,000.

关键词： Time series analysis Graphics processing units Computer architecture Big Data Feature extraction Data mining Artificial intelligence

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Research and Implementation of Binocular Image Stitching Algorithm Based on FPGA

Research and Implementation of Binocular Image Stitching Alg...

引用

Computer Vision, Image and Deep Learning (CVIDL), international conference on

作者： Zhenhui Yao Dingfeng Yu Weizhi Geng Hongfeng Zhang Yidong Xu Wei Xue Yantai Research Institute Harbin Engineering University Yantai China Wuhan Second Ship Design and Research Institute Wuhan China

ISBN: (数字)9798350373820

ISBN: (纸本)9798350373837

the underwater environment is complex and variable. Light propagation is affected by multiple factors, such as water absorption and scattering. this often results in a lack of brightness in underwater images, which can hinder the extraction of image features and affect the matching of feature points between subsequent images. Given the aforementioned issues, this paper proposes the use of the FPGA platform in conjunction with the ORB algorithm to enhance the original feature extraction and descriptor generation algorithm. the goal is to improve the effectiveness of the feature extraction algorithm under varying light intensities. Additionally, a new 64-bit descriptor is designed using the parallelism of the FPGA. False matching points are removed through statistical analysis, ultimately achieving feature matching between two underwater images.

关键词： Deep learning Concurrent computing Statistical analysis Scattering parallel processing Feature extraction Real-time systems

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Evaluating Attention in Convolutional Neural Networks for Blended Images

Evaluating Attention in Convolutional Neural Networks for Bl...

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international Image processing, Applications and Systems conference (IPAS)

作者： Andrea Portscher Sebastian Stabinger Antonio Rodríguez-Sánchez Department of Computer Science University of Innsbruck Innsbruck Austria

ISBN: (纸本)9781665462204

In neuroscientific experiments, blended images are used to examine how attention mechanisms in the human brain work. they are particularly suited for this research area, as a subject needs to focus on particular features in an image to be able to classify superimposed objects. As Convolutional Neural Networks (CNNs) take some inspiration from the mammalian visual system – such as the hierarchical structure where different levels of abstraction are processed on different network layers – we examine how CNNs perform on this task. More specifically, we evaluate the performance of four popular CNN architectures (ResNet18, ResNet50, CORnet-Z, and Inception V3) on the classification of objects in blended images. Since humans can rather easily solve this task by applying object-based attention, we also augment all architectures with a multi-headed self-attention mechanism to examine its effect on performance. Lastly, we analyse if there is a correlation between the similarity of a network architecture's structure to the human visual system and its ability to correctly classify objects in blended images. Our findings showed that adding a self-attention mechanism reliably increases the similarity to the V4 area of the human ventral stream, an area where attention has a large influence on the processing of visual stimuli.

关键词： Visualization Correlation Image processing Visual systems Streaming media Network architecture Convolutional neural networks

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Classification of Documents Using Machine Learning and Genetic algorithms 6th

Classification of Documents Using Machine Learning and Genet...

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6th international conference on Business Intelligence, CBI 2021

作者： Ahle Touate, Chaima Zougagh, Hicham Information Processing and Decision Support Laboratory Faculty of Sciences and Technics Sultan Moulay Slimane University Beni Mellal Morocco

ISBN: (纸本)9783030765071

In the past few years, there has been rampant growth in the amount of complex documents that stand in need of a deeper understanding of machine learning methods to classify them in many applications. the success of these methods depends on their ability to understand complex patterns and nonlinear relationships in data. Yet, finding the right structures, architectures, and techniques for text classification is often a challenge for researchers. In this article, we present an automated document classification system based on two axes;the first regard the processing of natural language (NLP), along with the second that focuses on Machine Learning (ML) algorithms. In addition, a hybrid system that combines the best of classification models in a single strong system with a very high percentage of accuracy that we came to give rise to with the genetic algorithms (GA). © 2021, Springer Nature Switzerland AG.

关键词： Natural language processing systems

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A High-Performance Architectural Design for FIR Filtering in Fixed and Reconfigurable Applications

A High-Performance Architectural Design for FIR Filtering in...

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Trends in Material Science and Inventive Materials (ICTMIM), international conference on

作者： Harikaran S Naveen Kumar G Sharmila J Kanagamalliga S Dept. of Electronics and Communication Engineering Saveetha Engineering College Chennai India

ISBN: (数字)9798331501488

ISBN: (纸本)9798331501495

the FIR filter architecture is proposed that achieves high-speed operation focused on both fixed and programmable applications. Instead, we take a transpose form configuration of a block FIR filter in an area-delay efficient way, which is effective for medium-to-large orders of the filters we introduce a generalized block formulation for transpose FIR filters, providing a unified approach for implementation. Moreover, we also present a low-complexity architecture based on the Multiple Constant Multiplication (MCM) strategy for fixed FIR filters, which helps in inordinate reduction in associated complexity and resources. the proposed architecture shows significant savings in terms of the Area-Delay Product (ADP), when compared to the traditional direct-form FIR filter architectures when they are implemented using digital blocks, which is especially true for medium and large sizes. the direct-form implementation is more efficient for low filter lengths, but as they increase, it becomes impractical, where the proposed architecture applies. this renders the design highly beneficial for reconfigurable and resource-efficient FIR filter applications. To verify the functionality of the proposed architecture, the design is coded in Verilog HDL, modeled in ModelSim and synthesized in Xilinx tools. Extensive experimental results validate that the proposed architecture save a huge amount with respect to resource usage as well as delay, thus are very beneficial for future digital signal processing applications. therefore, the proposed method offers a flexible and efficient design of fixed and reconfigurable FIR filters that meets the increasing demand for high-performance and low-complexity digital filter structures.

关键词： Materials science and technology Power demand Finite impulse response filters Computer architecture throughput Market research Real-time systems Complexity theory Hardware design languages Pipeline processing

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A Sequential Update Algorithm with parallel processing for Deep Learning-Based Beamforming in Real Environments 12

A Sequential Update Algorithm with Parallel Processing for D...

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12th international conference on ICT Convergence (ICTC) - Beyond the Pandemic Era with ICT Convergence Innovation

作者： Yoon, Sung-Wook Kwon, Oh-Wook Chungbuk Natl Univ Dept Intelligent Syst & Robot Cheongju South Korea

ISBN: (纸本)9781665423830

In this paper, we propose a deep learning-based sequential update beamforming algorithm for continuous speech enhancement in real environments. Previous beamforming algorithms have evaluated the performance using pre-segmented audio signals generated by mixing speech and noise in a completely overlapped manner. However, in real environments, speech utterances are sparsely uttered on the time axis and then input signals of beamformers become a continuous noisy speech stream with no speech most of the time. When a noise signal without speech is input to the previous beamforming algorithms, the performance is degraded. Considering these facts, we propose a robust block-wise sequential update algorithm in the real environment. In addition, by using parallel processing, the convergence speed of the update algorithm was increased, resulting in additional performance improvement. the evaluation set is composed of a mixture of speech utterances extracted from the CHiME3 evaluation set and the continuously-played background music extracted from MUSDB. As a speech recognizer, the Kaldi-based toolkit is used. We confirm that the proposed sequential update beamforming algorithm shows better performance than the baseline beamforming algorithm.

关键词： beamforming deep learning sequential update algorithm

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FPGA Implementation of 32-Bit parallel LMS Adaptive Beamforming Architecture using Two 8-Bit Stages

FPGA Implementation of 32-Bit Parallel LMS Adaptive Beamform...

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international conference on Computing and Networking Technology (ICCNT)

作者： Mohini R. Damodar Yogita Vaidya Electronics and Telecommunication VLSI & Embedded system COEP Technological university Pune India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this research project analyses a hardware pipelined reduced complexity parallel least mean square (RC-pLMS) implementation for adaptive beamforming. the composite of every single stage of defects in RC-pLMS, which is composed of two massively parallel, least mean square (LMS) phases, produces the overall error signal (pLMS). By removing the second independent weight set, the pLMS has been further reduced in size, ending in a less complex pLMS architecture (RC-pLMS). Our proposed RCpLMS algorithm (DRC-pLMS) will utilise a pipelined hardware architecture because to this approach alongside the delay and sum relaxation approach. Synthesise and implementation outcomes show that the recommended design delivers a maximum operational frequency and its take maximum resource utilisations. the objective of this study is to improve efficiency by switching the DRC-pLMS design with two 8-bit input levels. At the end, this work was translated into Verilog HDL, produced on a Xilinx Vertex-5 FPGA, and all the parameters related to area, delay, and power were compared.

关键词： Frequency synthesizers Array signal processing Adaptive algorithms Mean square error methods Hardware Delays Hardware design languages Field programmable gate arrays Adders Convergence

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5th international Symposium on Intelligent Computing Systems, ISICS 2024

5th International Symposium on Intelligent Computing Systems...

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5th international Symposium on Intelligent Computing Systems, ISICS 2024

ISBN: (纸本)9783031829307

the proceedings contain 25 papers. the special focus in this conference is on Intelligent Computing Systems. the topics include: Using LLMs to Enhance Research Output Tracking in Weakly Categorized Research Areas: A Case Study to Classify Publications in Islamic Economics, Finance, Banking and Business;Evaluating AI-Generated Video Quality: A Novel Assessment Model;a Non-blind Audio Watermarking in 3D Mesh Models Using Daubechies Wavelet Technique;Assessing the Impact of Data Augmentation Techniques on YOLO’s Performance in PV Anomaly Detection;studying Factors Affecting Attitudes on Artificial Intelligence Voice Assistants in the United Arab Emirates;Conceptualizing a Generative AI-Based Solution for Emotional Intelligence Interventions: Application to Education and Training;dental Caries Segmentation from Orthopantomograms Using Optimized DeepLabV3+;convolutional Neural Networks for the Classification of Comet Assay Cells;AI Driven Carbon Emission Estimation and Forecasting with Recommended Solution;leveraging Deep Learning for Accurate Classification of Leptograpsus Crabs Based on Morphological Measurements;heart Disease Prediction Using Machine Learning;development and Implementation of a Learning Management System with Data Analytics for Enhanced Online Education;VidLyze: Video Content Toxicity Identification Tool Using Natural Language processing (NLP) and Machine Learning;Comprehensive Evaluation of GAN architectures for Acute Lymphoblastic Leukemia Classification;a Novel Classification of Authentication Schemes for Internet of Drones;carbonMetric: An Intelligent System for Calculating and Reducing Carbon Footprints in Urban Environments;evaluating Adan vs. Adam: An Analysis of Optimizer Performance in Deep Learning;quality Assessment of Fundus Images for Further Classification: Lesson from thesis;empowering Students: Leveraging No-Code and Training Models with Google Machine Learning for Accessible App Development.

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parallel Approach to Sliding Window Sums 19th

Parallel Approach to Sliding Window Sums

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Snytsar, Roman Turakhia, Yatish Microsoft Corp One Microsoft Way Redmond WA 98052 USA Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9783030389611;9783030389604

Sliding window sums are widely used for string indexing, hashing, time series analysis and machine learning. New vector algorithms which utilize the advanced vector extension (AVX) instructions available on modern processors, or the parallel compute units on GPUs and FPGAs, would provide a significant performance boost. We develop a generic vectorized sliding sum algorithm with speedup for window size w and number of processors P is O(P/w) for a generic sliding sum. For a sum with commutative operator the speedup is improved to O(P/log(w)). Implementing the algorithm for the bioinformatics application of minimizer based k-mer table generation using AVX instructions, we obtain a speedup of over 5x.

关键词： Time series analysis

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SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems 22

SPAMeR: Speculative Push for Anticipated Message Requests in...

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Proceedings of the 51st international conference on parallel processing

作者： Qinzhe Wu Ashen Ekanayake Ruihao Li Jonathan Beard Lizy John University of Texas at Austin United States of America Arm United States of America

ISBN: (纸本)9781450397339

With increasing core counts and multiple levels of cache memories, scaling multi-threaded and task-level parallel workloads is continuously becoming a challenge. A key challenge to scaling the number of communicating tasks (or threads) is the rate at which existing communication mechanisms scale (in terms of latency and bandwidth). architectures with hardware accelerated queuing operations have the potential to reduce the latency and improve scalability of moving data between processing elements, reducing synchronization penalties, and thereby improving the performance of task-level parallel workloads. While hardware queues reduce synchronization penalties, they cannot fully hide load-to-use latency, i.e., perfect pipelines often are not realized. there is the potential, however, for better overlap. If the inter-processor communication latency is equal to or less than the time spent processing a message at the consumer, any and all latency may be overlapped while the consumer is processing. We exploit this property to speedup parallel applications above and beyond existing hardware queues. In this paper, we present SPAMeR, a speculation mechanism built on top of a state-of-the-art hardware-driven message queue architecture. SPAMeR has the capability to speculatively push messages in anticipation of consumer message requests. Unlike pre-fetch approaches which predict what addresses to fetch next, with a queue we know exactly what data is needed next but not when it is needed; SPAMeR adds algorithms that attempt to predict this. We evaluate the effectiveness of SPAMeR with a set of diverse task-parallel benchmarks utilizing the gem5 full system simulator, and observe a 1.33 × average speedup.

关键词： parallel computing message queue multi-core system speculation

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