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5th international conference on Advanced Machine Learning Technologies and Applications, AMLTA 2020

作者： Mahadevaswamy, U.B. Shashank Rao, M. Vrushab, S. Anagha, C. Sangameshwar, V. Department of Electronics and Communication Engineering Sri Jayachamarajendra College of Engineering Mysuru India

ISBN: (纸本)9789811533822

Lip reading is the ability to understand what a person is communicating using just the video information. Due to the advent of Internet and computers, it is now possible to remove human intervention from lip reading. Such automation is only feasible because of a couple of developments in the field of computer vision: availability of a large-scale dataset for training and use of neural network models. the applications to this are numerous. From dictating messages to a device in a noisy environment to improving speech recognition in the current technologies, visual speech recognition has proved to be pivotal. In this paper, the lip-reading models are based on deep neural network architectures that capture temporal data which are created for the task of speech recognition. © Springer Nature Singapore Pte Ltd 2021.

关键词： Speech recognition

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Lightweight Hardware architectures for the Piccolo Block Cipher in FPGA 5

Lightweight Hardware Architectures for the Piccolo Block Cip...

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5th international conference on Advanced Technologies for Signal and Image processing (ATSIP)

作者： Mhaouch, Ayoub Elhamzi, Wajdi Atri, Mohamed Univ Monastir Fac Sci Monastir Lab Elect & Microelect E E Monastir Tunisia Prince Sattam bin Abdulaziz Univ Coll Comp Engn & Sci Al Kharj Saudi Arabia Univ Sousse Higher Sch Sci & Technol Hammam Sousse Sousse Tunisia King Khalid Univ Coll Comp Sci Abha Saudi Arabia

ISBN: (纸本)9781728175133

the Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. the proposed implementation was performed on Xilinx Spartan-3. the iterative implementation achieves 76% of resource utilization. this implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. the serial implementation was optimized in terms of area to reduce the cost. It achieves 54% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps.

关键词： lightweight block cipher Piccolo block cipher FPGA Cryptography Hardware architectures low area VHDL

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Classification of Human Indoor Activities with Resource Constrained Network architectures on Audio Data

Classification of Human Indoor Activities with Resource Cons...

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international IEEE conference and Workshop: Óbuda on Electrical and Power Engineering (CANDO-EPE)

作者： Joseph Anand Marcel Koch Fabian Schlenke Fabian Kohlmorgen Hendrik Wöhrle Department of Information Technology Dortmund University of Applied Sciences and Arts Dortmund Germany

ISBN: (纸本)9798350346206

Many functions and processes in Smart Homes can be improved by incorporating knowledge about the activities of the inhabitants. the inhabitant activities can be recognized by classifying typical sounds related to the activities using audio classification methods. In this paper, we present and approach for the classification of activity-based audio data, taking into account that in many cases the data processing has to be deployed on a resource-constrained device. An indoor dataset is created by recording 11 distinct human actions that are typically perfomed in a living room and kitchen setup. A Convolutional Neural Network (CNN) is used for classification that achieves an accuracy of up to 98%. In addition, network optimization methods like depthwise separable convolutions, pruning, channel scaling and quantization is used to reduce the memory footprint and computational requirements to obtain an optimized network with 93% fewer Million Floating point Operations (MFLOPs) and less than 2% drop in accuracy is achieved for use in resourceconstrained devices.

关键词： Power engineering Quantization (signal) conferences Memory management Optimization methods Smart homes Network architecture

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Multi-fold Scheduling Algorithm for Multi-core Multi-Processor Systems

Multi-fold Scheduling Algorithm for Multi-core Multi-Process...

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5th international conference on Computing, Communication and Security (ICCCS)

作者： Gautam, Savita Umar, M. Sarosh Samad, Abdus Aligarh Muslim Univ Univ Womens Polytech Aligarh Uttar Pradesh India

ISBN: (纸本)9781728191805

Adapting parallel scheduling function in the design of multi-scheduling algorithm results significant impact in the operation of high performance parallel systems. the various methods of parallelizing scheduling functions are widely applied in traditional multiprocessor systems. In this paper a novel algorithm is introduced which works not only for parallel execution of jobs but also focuses the parallelization of scheduling function. It gives attention on reducing the execution time, minimizing the load balance performance by selecting the volume of tasks for migration in terms of packets. Jobs are grouped into packets consisting of 2(n) jobs which are scheduled in parallel. thus, an enhancement in the scheduling mechanism by packet formation is made to carry out high utilization of underlying architecture with increased throughput. the proposed method is assessed on a desktop computer equipped with multi-core processors in cube based multiprocessor systems. the algorithm is implemented with different configuration of multi-core systems. the simulation results indicate that the proposed technique reduces the overall makespan of execution with an improved performance of the system.

关键词： packet scheduling multicore load imbalance factor execution time task migration cube architectures

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A Multibeam Antenna for Multi-Orbit LEO Satellites and Terminals with a Very Simple Tracking Technique

A Multibeam Antenna for Multi-Orbit LEO Satellites and Termi...

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international conference on Communications, Signal processing, and their Applications (ICCSPA)

作者： Mohamed Sanad Noha Hassan Faculty of Engineering Cairo University

ISBN: (纸本)9781665482387

A foldable/deployable multi-beam antenna has been developed for Low-Earth Orbit (LEO) satellites and ground stations. It consists of dual parabolic cylindrical reflectors with multiple resonant feeds. It can generate an arbitrary number of beams with arbitrary vertical and horizontal beam-tilt for each beam. It can be remotely controlled to cover any arbitrary area having any shape/size. It has a very wide frequency band-width. It can even, simultaneously, work at multi wide frequency bands such as 5G-sub-6GHz band (3.3-6.0 GHz), Ku-band (10–16 GHz) and Ka-band (18–31 GHz). A very simple beam tracking technique has been developed without using any adaptive methods. For any specific satellite orbit, the orientation of the ground station (terminal) antenna will always be adjusted such that its generated beams are parallel to the satellite's beams and directed toward them. this automatic orientation of the ground station (terminal) antenna, completely, depends on its location, orientation and elevation with no need for any adaptive beam steering/tracking or any adaptive beam-shaping. Furthermore, the terminal antenna can simultaneously communicate with multiple satellites in different orbits. For example, a penta beam terminal antenna can, simultaneously, communicate with five satellites in five different orbits.

关键词： Satellite antennas Satellites Low earth orbit satellites Adaptive arrays Resonant frequency Switches Signal processing

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Studying the Performance of Vector-Based Quicksort Algorithm 13th

Studying the Performance of Vector-Based Quicksort Algorithm

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13th international conference on parallel processing and Applied Mathematics, PPAM 2019

作者： Marowka, Ami Parallel Research Lab Jerusalem Israel

ISBN: (纸本)9783030432218

the performance of parallel algorithms is often inconsistent with their preliminary theoretical analyses. Indeed, the difference is increasing between the ability to theoretically predict the performance of a parallel algorithm and the results measured in practice. this is mainly due to the accelerated development of advanced parallel architectures, whereas there is still no agreed model for parallel computation, which has implications for the design of parallel algorithms. In this study, we examined the practical performance of Cormen’s Quicksort parallel algorithm. We determined the performance of the algorithm with different parallel programming approaches and examine the capacity of theoretical performance analyses of the algorithm for predicting the actual performance. © 2020, Springer Nature Switzerland AG.

关键词： Python

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Effect of ultrasound on parallel flow in a microchannel

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CHEMICAL ENGINEERING AND processing-PROCESS INTENSIFICATION 2022年 171卷 108465-108465页

作者： John, Jinu Joseph Van Gerven, Tom Katholieke Univ Leuven Dept Chem Engn Proc Engn Sustainable Syst ProcESS Leuven Belgium

Ultrasound and microreactors are a proven combination with many complementary effects that could lead to substantial improvement in an unit operation. this combination is especially effective in heterogeneous systems where the effectivity depends on improved mass transfer. this work focuses on immiscible liquid-liquid system for the purpose of reactive extraction. Since different flow patterns can be generated in a microreactor, a majority of the work with this combination focuses on the slug flow which is the most common and effective of the flow patterns. this work focuses on parallel flow which is less common due to the stricter conditions required to generate it, but with a more consistent interfacial area in comparison to the slug flow. the qualitative and quantitative effects of using ultrasound to parallel flow is explored with a high speed camera and a model test reactive extraction process. the effect of ultrasonic and operating parameters were studied. An improvement of 2.2 to 2.3 times in yield was obtained at a frequency of 41.57 kHz, amplitude of 590 mV and net applied elec. power of 20 W for a residence time ranging from 2 to 20 s, respectively.

关键词： parallel flow

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Survey of FPGA Methodology Considering High Performance Design Implementation

Survey of FPGA Methodology Considering High Performance Desi...

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international conference on ent Computing and Control Systems (ICICCS)

作者： Geetanjali Udgirkar CMR Institute of Technology Bengaluru India

the most popular platform emerging for the implementation of complex engineering algorithms is Field programmable gate arrays (FPGAs) due to their parallelism of implementation and flexibility in the design architecture. However, in order to achieve great performance, the FPGA must have design methodology and optimization techniques which are effective and efficient. this paper presents FPGA based design optimization techniques and methodology that are used to obtain speed, power and area.

关键词： Design methodology Computer architecture parallel processing Logic gates Hardware Energy efficiency Computational efficiency

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parallel Software Testing Sequence Generation Method Target at Full Covering Tested Behaviors 19th

Parallel Software Testing Sequence Generation Method Target ...

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Sun, Tao Wan, Xiaoyun Zhong, Wenjie Guo, Xin Zhang, Ting Inner Mongolia Univ Coll Comp Sci Hohhot 100021 Inner Mongolia Peoples R China

ISBN: (纸本)9783030389611;9783030389604

parallel software system testing is very difficult because the number of states expands sharply caused by parallel behaviors. In this paper, a testing sequence generation method is proposed, target at full covering tested behaviors and related behaviors over all execution paths. Because of state spaces of parallel software systems are often large, this paper focuses on the state space subgraph, contained all firing of tested and related behaviors, of system model. Firstly, the software system is modeled with Colored Petri Net (CPN), called system model (SM), and every tested behavior or related behavior is modeled also with CPN, called Behavior Model Unit (BMU). then, the method proposes mapping operation, intersection operation, and so on to finally realize the generation of test sequence. Practices show that this method is efficient, which could achieve full coverage.

关键词： parallel software Testing sequence generation Full covering Tested behaviors Colored Petri Net (CPN)

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FANG: Fast and Efficient Successor-State Generation for Heuristic Optimization on GPUs 19th

FANG: Fast and Efficient Successor-State Generation for Heur...

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Koester, Marcel Gross, Julian Krueger, Antonio Saarland Informat Campus Campus D3-2 D-66123 Saarbrucken Germany

ISBN: (纸本)9783030389918;9783030389901

Many optimization problems (especially nonsmooth ones) are typically solved by genetic, evolutionary, or metaheuristic-based algorithms. However, these genetic approaches and other related papers typically assume the existence of a neighborhood or successor-state function N(x), where x is a candidate state. the implementation of such a function can become arbitrarily complex in the field of combinatorial optimization. Many N(x) functions for a huge variety of different domainspecific problems have been developed in the past to solve this general problem. However, it has always been a great challenge to port or realize these functions on a massively-parallel architecture like a Graphics processing Unit (GPU). We present a GPU-based method called FANG that implements a generic and reusable N(x) for arbitrary domains in the field of combinatorial optimization. It can be customized to satisfy domainspecific requirements and leverages the underlying hardware in a fast and efficient way by construction. Moreover, our method has a high scalability with respect to the number of input states and the complexity of a single state. Measurements show significant performance improvements compared to traditional exploration approaches leveraging the CPU on our evaluation scenarios.

关键词： Heuristic search Combinatorial optimization Successor-state generation Neighborhood exploration Massively-parallel processing Graphics processing units GPUs

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