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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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5th international conference on Intelligent Computing and Applications, ICICA 2019

5th International Conference on Intelligent Computing and Ap...

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5th international conference on Intelligent Computing and Applications, ICICA 2019

ISBN: (纸本)9789811555657

the proceedings contain 71 papers. the special focus in this conference is on Intelligent Computing and Applications. the topics include: Performance Estimation and Analysis Over the Supervised Learning Approaches for Motor Imagery EEG Signals Classification;fully Automated Digital Mammogram Segmentation;empirical Study of Computational Intelligence Approaches for the Early Detection of Autism Spectrum Disorder;Intelligent Monitoring of Bearings Using Node MCU Module;image Denoising Using Various Image Enhancement Techniques;energy Consumption Analysis and Proposed Power-Aware Scheduling Algorithm in Cloud Computing;relationship Between Community Structure and Clustering Coefficient;digital Image Forensics-Image Verification Techniques;energy Efficient Data Centre Selection Using Service Broker Policy;using Automated Predictive Analytics in an Online Shopping Ecosystem;design and Development of Home Automation System;performance Analysis Study of Stochastic Computing Based Neuron;Scheduling of parallel Tasks in Cloud Environment Using DAG MODEL;GREENIE—Smart Home with Smart Power Transmission;ANAVI: Advanced Navigation Assistance for Visually Impaired;thIRD EYE—Shopfloor Data processing and Visualization Using Image Recognition;A Hybrid Search Group Algorithm and Pattern Search Optimized PIDA Controller for Automatic Generation Control of Interconnected Power System;Fractional Order PID Controlled PV Fed Quadratic Boost Converter TZ Source Inverter Fed Permanent Magnet Brushless Motor Drive;co-ordinate Measurement of Roll-Cage Using Digital Image processing;peformance Analysis of Joysticks Used in Infotainment Control System in Automobiles;Probabilistic Principal Component Analysis (PPCA) Based Dimensionality Reduction and Deep Learning for Cancer Classification;blockchain Technology for Data Sharing in Decentralized Storage System;Understanding Concepts of Blockchain Technology for Building the DApps;chennai Water Crisis—Data Analysis.

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Ultra Low Power High Speed DFT Implementation For ASIC SoC

Ultra Low Power High Speed DFT Implementation For ASIC SoC

引用

international conference for Convergence of Technology (I2CT)

作者： K. Madhava Rao Pattem Sampath Kumar T. Vasudeva Reddy D Nilima K Saikumar Abbas Mahdi Khlaif Dept of ECE B V Raju Institute of Technology Narsapur Medak Telangana Department of ECE Malla Reddy College of Engineering Maisammaguda Dhulapally Secunderabad Department of Computer Science and Information Technology MLR Institute of Technology Hyderabad Telangana India Computer Science School of Engineering Malla Reddy University Maisammaguda Dulapally Hyderabad Telangana Scientific Research Center Al-Ayen University Thi-Qar Iraq

ISBN: (数字)9798350394474

ISBN: (纸本)9798350394481

An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4k/8k points, a necessity in today's 4G and 5G communication technologies, which are plagued by a number of power and performance concerns with DFT processors. these technologies are widely used but have a higher energy footprint than others. Consequently, this work uses a novel approach called "SBOX" and the concept of parallelism to boost performance and reduce power consumption, all of which are essential for an advanced DFT architecture. parallelism and the proposed SBOX model allow for fewer multiplications and faster processing times. Cadence-allegro-17.2 is used for the design and verification of the full implementation; this software is also used for simulation, synthesis, layout, and power analysis. the area required for 8-point s-box DFT is 105.15 um2, it requires 7mW of power, and it can achieve a throughput of 59.33GBPS. In addition, the throughput of 57.33GBPS may be achieved by 16-point s-box DFT with a footprint of 123.35um2, using 9mW of power. Also, the throughput of 32-point s-box DFT is 56.45GBPS on a chip that uses 10.24 mW and occupies 132.35um2. With MIMO in 5G technology, this layout becomes more practical for usage in telecommunications. the performance is enhanced over existing architectures thanks to the optimized radix 8 s-box DFT.

关键词： 5G mobile communication Discrete Fourier transforms Layout Computer architecture parallel processing throughput Software

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A parallel Approach to Advantage Actor Critic in Deep Reinforcement Learning 19th

A Parallel Approach to Advantage Actor Critic in Deep Reinfo...

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhu, Xing Du, Yunfei Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou Peoples R China

ISBN: (纸本)9783030389611;9783030389604

Deep Reinforcement learning (DRL) algorithms recently still take a long time to train models in many applications. parallelization has the potential to improve the efficiency of DRL algorithms. In this paper, we propose an parallel approach (ParaA2C) for the popular Actor-Critic (AC) algorithms in DRL, to accelerate the training process. Our work considers the parallelization of the basic advantage actor critic (Serial-A2C) in AC algorithms. Specifically, we use multiple actor-learners to mitigate the strong correlation of data and the instability of updating, and finally reduce the training time. Note that we assign each actor-learner MPI process to a CPU core, in order to prevent resource contention between MPI processes, and make our ParaA2C approach more scalable. We demonstrate the effectiveness of ParaA2C by performing on Arcade Learning Environment (ALE) platform. Notably, our ParaA2C approach takes less than 10 min to train in some commonly used Atari games when using 512 CPU cores.

关键词： Deep reinforcement learning Advantage actor critic parallelization MPI Scalable

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RNC: Efficient RRAM-aware NAS and Compilation for DNNs on Resource-Constrained Edge Devices

RNC: Efficient RRAM-aware NAS and Compilation for DNNs on Re...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Kam Chi Loong Shihao Han Sishuo Liu Ning Lin Zhongrui Wang Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong China ACCESS - AI Chip Center for Emerging Smart Systems Hong Kong Science Park Hong Kong China School of Astronautics Harbin Institute of Technology Harbin China School of Microelectronics Southern University of Science and Technology Shenzhen China

ISBN: (数字)9798350380408

ISBN: (纸本)9798350380415

Computing-in-memory (CIM) is an emerging computing paradigm, offering noteworthy potential for accelerating neural networks with high parallelism, low latency, and energy efficiency compared to conventional von Neumann architectures. However, existing research has primarily focused on hardware architecture and network co-design for large-scale neural networks, without considering resource constraints. In this study, we aim to develop edge-friendly deep neural networks (DNNs) for accelerators based on resistive random-access memory (RRAM). To achieve this, we propose an edge compilation and resource-constrained RRAM-aware neural architecture search (NAS) framework to search for optimized neural networks meeting specific hardware constraints. Our compilation approach integrates layer partitioning, duplication, and network packing to maximize the utilization of computation units. the resulting network architecture can be optimized for either high accuracy or low latency using a one-shot neural network approach with Pareto optimality achieved through the Non-dominated Sorted Genetic Algorithm II (NSGA-II). the compilation of mobile-friendly networks, like Squeezenet and MobilenetV3 small can achieve over 80% of utilization and over 6x speedup compared to ISAAC-like framework with different crossbar resources. the resulting model from NAS optimized for speed achieved 5x-30x speedup. the code for this paper is available at https://***/ArChiiii/rram_nas_comp_pack.

关键词： Computer architecture parallel processing Network architecture In-memory computing Solids Hardware Common Information Model (computing) Neural architecture search Low latency communication Genetic algorithms

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Automatic Optimization of Python Skeletal parallel Programs 19th

Automatic Optimization of Python Skeletal Parallel Programs

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Loulergue, Frederic Philippe, Jolan No Arizona Univ Sch Informat Comp & Cyber Syst Flagstaff AZ 86011 USA IMT Atlantique LS2N INRIA UBL Nantes France

ISBN: (纸本)9783030389918;9783030389901

Skeletal parallelism is a model of parallelism where parallel constructs are provided to the programmer as usual patterns of parallel algorithms. High-level skeleton libraries often offer a global view of programs instead of the common Single Program Multiple Data view in parallel programming. A program is written as a sequential program but operates on parallel data structures. Most of the time, skeletons on a parallel data structure have counterparts on a sequential data structure. For example, the map function that applies a given function to all the elements of a sequential collection (e.g., a list) has a map skeleton counterpart that applies a sequential function to all the elements of a distributed collection. Two of the challenges a programmer faces when using a skeleton library that provides a wide variety of skeletons are: which are the skeletons to use, and how to compose them? these design decisions may have a large impact on the performance of the parallel programs. However, skeletons, especially when they do not mutate the data structure they operate on, but are rather implemented as pure functions, possess algebraic properties that allow to transform compositions of skeletons into more efficient compositions of skeletons. In this paper, we present such an automatic transformation framework for the Python skeleton library PySke and evaluate it on several example applications.

关键词： Algorithmic skeletons Program transformation Python

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High-Performance Simulations on GPUs Using Adaptive Time Steps 20th

High-Performance Simulations on GPUs Using Adaptive Time Ste...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Koester, Marcel Gross, Julian Krueger, Antonio Saarland Informat Campus Campus D3-2 D-66123 Saarbrucken Germany

ISBN: (纸本)9783030602451;9783030602444

Graphics processing Units (GPUs) are widely spread nowadays due to their parallel processing capabilities. Leveraging these hardware features is particularly important for computationally expensive tasks and workloads. Prominent use cases are optimization problems and simulations that can be parallelized and tuned for these architectures. In the general domain of simulations (numerical and discrete), the overall logic is split into several components that are executed one after another. these components need step-size information which determines the number of steps (e.g. the elapsed time) they have to perform. Small step sizes are often required to ensure a valid simulation result with respect to precision and constraint correctness. Unfortunately, they are often the main bottleneck of the simulation. In this paper, we introduce a new and generic way of realizing high-performance simulations with multiple components using adaptive time steps on GPUs. Our method relies on a code-analysis phase that resolves data dependencies between different components. this knowledge is used to generate specially-tuned execution kernels that encapsulate the underlying component logic. An evaluation on our simulation benchmarks shows that we are able to considerably improve runtime performance compared to prior work.

关键词： Simulations parallel computing Adaptive time steps Graphics processing units GPUs

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ParaMoC: A parallel Model Checker for Pushdown Systems 19th

ParaMoC: A Parallel Model Checker for Pushdown Systems

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Wei, Hansheng Ye, Xin Shi, Jianqi Huang, Yanhong East China Normal Univ Natl Trusted Embedded Software Engn Technol Res C Shanghai Peoples R China Res Ctr Hardware Software Codesign Technol & Applicat Eng Shanghai Peoples R China Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China LIPN Paris France Paris Univ 7 Paris France

ISBN: (纸本)9783030389611;9783030389604

Model checking on Pushdown Systems (PDSs) has been extensively used to deal with numerous practical problems. However, the existing model checkers for pushdown systems are executed on the central processing unit (CPU), the performance is hampered by the computing power of the CPU. Compared with the CPU, the graphics processing unit (GPU) has more processing cores, which are suitable and efficient for parallel computing. therefore, it is very attractive to accelerate model checking of PDSs on the GPU. In this paper, we present a new parallel model checker, named ParaMoC, to speed up the performance of model checking problems for pushdown systems (PDSs). Moreover, we focus on how to use Graphics processing Units (GPUs) to accelerate the reachability verification and the LTL model checking of PDSs. the ParaMoC running on a state-of-the-art GPU can be 100 times faster than the traditional PDS model checker.

关键词： Graphics processing unit

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parallel processing of Multi-dimensional Matrix Multiplication for Dynamic Dataset

Parallel Processing of Multi-dimensional Matrix Multiplicati...

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international conference on Electrical Information and Communication Technology (EICT)

作者： Sarjil Shariar Md. Safayet Hossain K. M. Azharul Hasan Khulna University of Engineering & Technology (KUET) Khulna Bangladesh

ISBN: (纸本)9781665409070

Scientific and engineering computing demands multi-dimensional data processing in various domains including big data, machine learning, graph processing, object recognition, etc. In this paper, we process the multi-dimensional data model, also called high order tensor, with parallel computation on Graphics processing Unit (GPU). We introduce a dimension conversion technique to construct the Converted Matrix Structure (CMS) that transforms the n-dimensional tensor data into 2-dimensional matrix data with the dynamic memory allocation. With this scheme, we can extend the dimension size during runtime for the further inclusion of tensor elements. therefore the proposed scheme can handle the dynamic dataset that can expand during runtime. We also propose the parallel processing of matrix multiplication with the CMS scheme for improved and faster performance. To conduct the parallel processing of the multi-dimensional matrix multiplication (MDMMP), we first distribute the n-dimensional tensor elements on GPU threads to retrieve the 2-dimensional matrices, and then we process the Row-By-Column (RBC) wise multiplications of the matrices simultaneously. We perform these parallel processing in such a way that the load balance is ensured by the dynamic use of parallel threads based on the multi-dimensional data size. We found good speed up using our algorithm.

关键词： Tensors Runtime Instruction sets Heuristic algorithms Computational modeling Graphics processing units parallel processing

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A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures 5

A Hardware/Software Framework for the Integration of FPGA-ba...

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5th IEEE international conference on Smart Cloud (IEEE SmartCloud) / 5th IEEE international Symposium on Reinforcement Learning (IEEE ISRL)

作者： Steinert, Fritjof Kreowsky, Philipp Wisotzky, Eric L. Unger, Christian Stabernack, Benno Fraunhofer Inst Telecommun Heinrich Hertz Inst Berlin Germany CPU 24 7 GmbH Potsdam Potsdam Germany Univ Potsdam Embedded Syst Architectures Signal Proc Potsdam Germany

ISBN: (纸本)9781728165479

the need for high computing power has increased enormously in recent years, particularly in the field of image signal processing and machine learning applications, very powerful computing systems are required. It has been shown that homogeneous architectures in data centers work very inefficiently regarding these special applications, showing high latency of the response times and providing a very poor power efficiency. In order to integrate FPGA (Field Programming Gate Array)- as well as GPU-based accelerators into cloud computing infrastructures as compute nodes we present a generic hardware/software framework for using heterogeneous computing systems. A real industrial image processing application shows the acceleration achieved.

关键词： Heterogeneous Computing Accelerator FPGA Cloud Computing Resource Management

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Graph partitioning using heuristic kernighan-lin algorithm for parallel computing 5th

Graph partitioning using heuristic kernighan-lin algorithm f...

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5th international conference on Computing in Engineering and Technology, ICCET 2020

作者： Patil, Siddheshwar V. Kulkarni, Dinesh B. Department of Computer Science and Engineering Walchand College of Engineering SangliMH India Department of Information Technology Walchand College of Engineering SangliMH India

ISBN: (纸本)9789811548505

the goal of parallel computing is to distribute the load on available processors such that all processors should be utilized in a fair manner. this minimizes the overall execution time required to execute a complex task. So, the load balancing issue becomes an important aspect of parallel computing. It is abstracted as a graph partitioning problem in which the nodes represent computation cost, edges represent communication cost, and number of partitions should be equal to number of available processing units. So, the objective is to cut the graph into k-partitions such that—(i) total node weight should be equal for each partition and—(ii) minimize total edge weight across the partitions. A heuristic Kernighan-Lin graph partitioning algorithm for two-way partitioning is evaluated in this paper. It starts with an initial random graph partition and consecutively exchanges the nodes between partitions, determines cut size at each stage and saves the minimum cut found so far. After the desired number of swaps has been performed, the saved minimum cut will give optimal partitions. the graph data for experimental work is obtained from DIMACS tenth implementation challenge Web site. the experimental results show minimum cut-cost with respect to balance constraint. the results are compared with ground truth results for validation. © Springer Nature Singapore Pte Ltd 2021.

关键词： parallel processing systems

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