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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures 5

A Hardware/Software Framework for the Integration of FPGA-ba...

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5th IEEE international conference on Smart Cloud (IEEE SmartCloud) / 5th IEEE international Symposium on Reinforcement Learning (IEEE ISRL)

作者： Steinert, Fritjof Kreowsky, Philipp Wisotzky, Eric L. Unger, Christian Stabernack, Benno Fraunhofer Inst Telecommun Heinrich Hertz Inst Berlin Germany CPU 24 7 GmbH Potsdam Potsdam Germany Univ Potsdam Embedded Syst Architectures Signal Proc Potsdam Germany

ISBN: (纸本)9781728165479

the need for high computing power has increased enormously in recent years, particularly in the field of image signal processing and machine learning applications, very powerful computing systems are required. It has been shown that homogeneous architectures in data centers work very inefficiently regarding these special applications, showing high latency of the response times and providing a very poor power efficiency. In order to integrate FPGA (Field Programming Gate Array)- as well as GPU-based accelerators into cloud computing infrastructures as compute nodes we present a generic hardware/software framework for using heterogeneous computing systems. A real industrial image processing application shows the acceleration achieved.

关键词： Heterogeneous Computing Accelerator FPGA Cloud Computing Resource Management

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Graph partitioning using heuristic kernighan-lin algorithm for parallel computing 5th

Graph partitioning using heuristic kernighan-lin algorithm f...

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5th international conference on Computing in Engineering and Technology, ICCET 2020

作者： Patil, Siddheshwar V. Kulkarni, Dinesh B. Department of Computer Science and Engineering Walchand College of Engineering SangliMH India Department of Information Technology Walchand College of Engineering SangliMH India

ISBN: (纸本)9789811548505

the goal of parallel computing is to distribute the load on available processors such that all processors should be utilized in a fair manner. this minimizes the overall execution time required to execute a complex task. So, the load balancing issue becomes an important aspect of parallel computing. It is abstracted as a graph partitioning problem in which the nodes represent computation cost, edges represent communication cost, and number of partitions should be equal to number of available processing units. So, the objective is to cut the graph into k-partitions such that—(i) total node weight should be equal for each partition and—(ii) minimize total edge weight across the partitions. A heuristic Kernighan-Lin graph partitioning algorithm for two-way partitioning is evaluated in this paper. It starts with an initial random graph partition and consecutively exchanges the nodes between partitions, determines cut size at each stage and saves the minimum cut found so far. After the desired number of swaps has been performed, the saved minimum cut will give optimal partitions. the graph data for experimental work is obtained from DIMACS tenth implementation challenge Web site. the experimental results show minimum cut-cost with respect to balance constraint. the results are compared with ground truth results for validation. © Springer Nature Singapore Pte Ltd 2021.

关键词： parallel processing systems

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Finite-Field parallel Adder Circuit Over Prime Numbers Based on Spiking Neural P Systems 20th

Finite-Field Parallel Adder Circuit Over Prime Numbers Based...

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20th Mexican international conference on Artificial Intelligence (MICAI)

作者： Tonatihu Juarez-Velazquez, Emmanuel Hernandez-Lara, Derlis Alfonso Trejo-Villanueva, Carlos Inst Politecn Nacl Escuela Super Ingn Mecan & Elect Ciudad De Mexico Mexico Tecnol Nacl Mexico Tecnol Estudios Super Ecatepec Ecatepec de Morelos Ecatepec Estado Mexico

ISBN: (纸本)9783030898205;9783030898199

Nowadays, the arithmetic operations precision is one of the most critical aspects in the development of efficient finite-field arithmetic circuits, because they are involved in several applications, for example, in advanced cryptographic algorithms such as AES (Advanced Encryption Standard), elliptic curves and RSA (Rivest Shamir Adleman). Most of these algorithms have been implemented on general purpose machines. However, the performance of recent computational systems could not satisfy the computational needs to perform finite-field arithmetic computations of large bit-length numbers, because the word length of these processors is too small compared with the bit-length of these numbers and thus suffer from the resulting increase in execution time. One potential solution can be found in the development of advanced highly parallel computing systems. Recently, an emerging branch of natural computation has created arithmetic circuits based on parallel computing (Spiking Neural P Systems). Most of them perform basic arithmetic operations sequentially despite of having intrinsic parallelism. In this paper, we introduce for the first time, the design of a finite-field parallel adder circuit, which is highly inspired by neural processing of the soma, synaptic weights and rules on the synapses, to process numbers with large bit-length efficiently.

关键词： parallel adder Finite-field Spiking neural P system (SN P)

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Tight Bound of parallel Request Latency for Erasure-Coded Distributed Storage System 20th

Tight Bound of Parallel Request Latency for Erasure-Coded Di...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zou, Xingshun Li, Wei Shandong Univ Jinan Peoples R China

ISBN: (纸本)9783030602451;9783030602444

With big data analysis and cloud storage improving at an astonishing rate in recent years, more and more parallel computing and data analysis techniques are invented and applied to accessing data from a distributed storage system, which has noticeable differences with accessing data from a separate dedicated storage system. the first and the last processes of a data analysis task in a shared filesystem may have a remarkable gap in latency. the latency of parallel file requests from these processes, however, lacks analytical model especially when erasure code is employed as storage strategy. the main contribution of this work is development of a tight bound of parallel file request latency to give a theoretical upper bound of lantency. Additionally, an exact batch file chunk request analytical model in distributed systems adopting erasure code is studied by the technique of two embedded Markov chains, performance measures such as queue length distribution, waiting time distribution, etc. are derived in closed form. Experimental evaluation verifies accuracy of the theoretical upper bound on latency.

关键词： parallel file requests Distributed storage system Erasure code Queueing theory Latency Embedded Markov chain

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Single Node Acceleration of Generative Adversarial Networks using HPC for Image Analytics 22

Single Node Acceleration of Generative Adversarial Networks ...

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Proceedings of the 2022 5th international conference on Computational Intelligence and Intelligent Systems

作者： Aswathy Ravikumar Harini Sriraman School of Computer Science and Engineering Vellore Institute of Technology India

ISBN: (纸本)9781450397612

Generative Adversarial Networks (GAN) are approaches that are utilized for data augmentation, which facilitates the development of more accurate detection models for unusual or unbalanced datasets. Computer-assisted diagnostic methods may be made more reliable by using synthetic pictures generated by GAN. Generative adversarial networks are challenging to train because too unpredictable training dynamics may occur throughout the learning process, such as model collapse and vanishing gradients. For accurate and faster results the GAN network need to trained in parallel and distributed manner. We enhance the speed and precision of the Deep Convolutional Generative Adversarial Networks (DCGAN) architecture by using its parallelism and executing it on High-Performance Computing platforms. the effective analysis of a DCGAN in Graphic processing Unit and Tensor processing Unit platforms in which each layer execution pattern is analyzed. the bottleneck is identified for the GAN structure for each execution platforms. the Central processing Unit is capable of processing neural network models, but it requires a great deal of time to do it. Graphic processing Unit in contrast, side, are a hundred times quicker than CPUs for Neural Networks, however, they are prohibitively expensive compared to CPUs. Using the systolic array structure, TPU performs well on neural networks with high batch sizes but in GAN the shift between CPU and TPU is huge so it does not perform well.

关键词： Generative Adversarial Network High-Performance Computing Graphic processing Unit Tensor processing Unit

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HDF5-Based I/O Optimization for Extragalactic HI Data Pipeline of FAST 19th

HDF5-Based I/O Optimization for Extragalactic HI Data Pipeli...

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Ji, Yiming Yu, Ce Xiao, Jian Tang, Shanjiang Wang, Hao Zhang, Bo Tianjin Univ Coll Intelligence & Comp Tianjin Peoples R China Chinese Acad Sci CAS Key Lab FAST NAOC Beijing Peoples R China

ISBN: (纸本)9783030389611;9783030389604

the Five-hundred-meter Aperture Spherical Radio Telescope (FAST), which is the largest single-dish radio telescope in the world, has been producing a very large data volume with high speed. So it requires a high performance data pipeline to covert the huge raw observed data to science data product. However, the existing solutions of pipelines widely used in radio data processing cannot tackle this situation efficiently. the paper proposes a pipeline architecture for FAST based on HDF5 format and several I/O optimization strategies. First, we design the workflow engine driving the various tasks efficiently in the pipeline;second, we design a common radio data storage specification on the top of HDF5 format, and also developed a fast converter to map the original FITS format to the new HDF5 format;third, we apply several concrete strategies to optimize the I/O operations, including chunks storage, parallel reading/writing, on-demand dump, and stream process etc. In the experiment of processing 700 GB of FAST data, the results show that HDF5 based data structure without other optimizations was 1.7 times faster than original FITS format. If chunk storage and parallel I/O optimization are applied, the overall performance can reach 4.5 times as the original one. Moreover, due to the good expansibility and flexibility, our solution of FAST pipeline can be adapted to other radio telescopes.

关键词： FAST FITS HDF5 Pipeline in parallel High performance I/O

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On the Performance of SC-Flip and SC-Perturbation Decoders for parallel Decoding of Polar Codes 12

On the Performance of SC-Flip and SC-Perturbation Decoders f...

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12th international conference on ICT Convergence (ICTC) - Beyond the Pandemic Era with ICT Convergence Innovation

作者： Park, Jisang Ju, Hyosang Yoon, Chanho Cho, Woncheol Kim, Sang-Hyo Sungkyunkwan Univ Dept Elect & Comp Engn Suwon South Korea ETRI Future Mobile Commun Res Div Res Lab Daejeon South Korea

ISBN: (纸本)9781665423830

In ultra-high frequency band communication for 5G or beyond 5G, high-speed transmission of the Tbps-level is targeted [1]. To reach that level, parallelization of decoding algorithms and architecture is crucial. there have been studies that have implemented the high-speed polar decoder, but it was possible to implement only under compromise in the error-rate performance, because of the use of successive cancellation (SC) decoding [2] instead of SC-list (SCL) [3] decoding. therefore, it is essential to study decoder with improved performance whose performance can be comparable to the SCL decoder while using the SC decoder. the SC-Flip (SCF) [4]-[6] and SC-Perturbation (SCP) decoding [7], [8] as post-processing decoding techniques, improve the performance through re-decoding when the initial SC decoding fails. As the signal-to-noise ratio (SNR) increases, the average complexity converges to the SC decoding level while attaining better error-rate performance than the SC decoder. However, the performance of this post-processing schemes has not been compared nor extensively investigated. therefore, we analyze the performance of SCF and SCP decoders with respect to the maximum number of decoding iterations for various coding parameters. We confirm that the SCF is better when the maximum number of decoding iterations is small, and the SCP outperforms the SCF as the number of iteration increases.

关键词： Successive cancellation decoding flip decoding perturbation decoding polar codes

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parallel Multiobjective Feature Selection for Binary Classificatio 5

Parallel Multiobjective Feature Selection for Binary Classif...

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5th international conference on Computer Science and Engineering (UBMK)

作者： Deniz, Ayca Kiziloz, Hakan Ezgi Middle East Tech Univ Comp Engn Dept Ankara Turkey Univ Turkish Aeronaut Assoc Comp Engn Dept Ankara Turkey

ISBN: (纸本)9781728175652

Feature selection has become a prominent step for many research studies as available data increases continuously with the advances in technology. the objective of feature selection is two-fold: minimizing the number of features and maximizing learning performance. therefore, it requires a multi-objective optimization. In this study, we utilize the multi-core nature of a regular PC in the feature selection domain. For this purpose, we build three models that exploit the parallel processing capability of a modern CPU. We execute the feature selection task on a single processor in the first model as a baseline. In other models, we execute the feature selection task in four cores of the CPU, in parallel. Specifically, in the second model, we decrease the population size per processor and explore whether we can achieve comparable solution sets in less amount of time. the third model preserves the population size and explores a more extensive search space. We compare the results of these models in terms of accuracy, number of features and execution time. Experiment results show that parallel processing in the feature selection domain leads to faster execution and better feature subsets.

关键词： Feature selection Multiobjective optimization parallel processing

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parallel Belief Propagation Optimized by Coloring on GPUs 20th

Parallel Belief Propagation Optimized by Coloring on GPUs

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Hou, Junteng Si, Chengxiang Wang, Shupeng Wu, Guangjun Zhang, Lei Chinese Acad Sci Inst Informat Engn Beijing Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing Peoples R China Coordinat Ctr China Natl Comp Network Emergency Response Tech Team Beijing Peoples R China

ISBN: (纸本)9783030602451;9783030602444

Belief propagation (BP) is a message passing algorithm that infers over probabilistic graphical models. Its main computational workload, messages update, is suitable for GPU's massively parallel architecture. However, the efficiency of fully parallel BP is low, and traditional algorithms implemented on GPUs occupy amount of computing and memory resources. In this paper, we propose several GPU-friendly BP algorithms optimized by coloring. Color Wave (CW) algorithm performs multi-step coloring on residuals of non-convergent vertices to quickly obtain multiple disjoint partitions and vertices with the largest residuals in each partition, and then updates batches of messages in a fixed order. these operations are all suitable for parallelization and require little additional memory. To save time in each iteration, the Color Extract (CE) algorithm only update messages on edges with the largest residuals among all adjacent edges. the Random Drop (RD) algorithm steadily increases the convergence degree by progressively reducing the messages update ratio of non-convergent edges. the experiments on different GPUs show that our algorithms perform well throughout the calculation process. Compared with state-of-the-art algorithms, CW algorithm converged most of the messages in previous iterations. the convergence degree of CE is higher than all other algorithms in most calculation processes. RD converges fast and always has a high degree of convergence.

关键词： Belief propagation GPUs parallel optimization Coloring operations Progressively reducing update ratio

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A Binary Code Sequence Based Tracking Algorithm in Wireless Sensor Networks 19th

A Binary Code Sequence Based Tracking Algorithm in Wireless ...

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhang, Yang Ren, Qianqian Pan, Yu Li, Jinbao Heilongjiang Univ Key Lab Database & Parallel Comp Heilongjiang Pro Harbin Peoples R China Heilongjiang Univ Key Lab Elect Engn Coll Heilongjiang Prov Harbin Peoples R China Heilongjiang Univ Sch Comp Sci & Technol Harbin Peoples R China

ISBN: (纸本)9783030389611;9783030389604

this paper proposes a binary code sequence based tracking algorithm in wireless sensor network. the proposed algorithm can release the influence of sensed data on localization results via building the map between target's occurrence region and a binary code sequence. To solve the ambiguity problem existing in occurrence region determination, the paper further gives a Voronoi diagram based location refinement algorithm. the simulation results show the tracking results under difference trajectories.

关键词： Target localization RSSI Voronoi

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