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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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Comparison of Synchronous and Asynchronous FIR Filter architectures 5

Comparison of Synchronous and Asynchronous FIR Filter Archit...

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5th international conference on Event-Based Control, Communication, and Signal processing (EBCCSP)

作者： Decoudu, Yoan Simatic, Jean Alexandre, Pauline Morin-Allory, Katell Fesquet, Laurent Univ Grenoble Alpes CNRS Grenoble INP Inst EngnTIMA F-38000 Grenoble France HawAI Tech F-38000 Grenoble France

ISBN: (纸本)9781728123226

the Internet of things requires developing ultra-low power platforms embedding actuators, sensors, and signal processors. In order to limit the power consumption of such systems, nonuniform sampling schemes are very promising solutions, especially if coupled to event-driven circuitries. this strategy allows reducing the amount of sampled data, the system activity, and then the power consumption. Moreover, High-Level Synthesis (HLS) helps designers in rapidly developing ultra-low power platforms. In this article, we present a comparison of the uniform and non-uniform schemes in term of activity and power consumption. this evaluation is performed on Finite Impulse Response (FIR) filters in three different flavors: a synchronous filter using a classical sampling scheme and two asynchronous filters implementing a nonuniform sampling scheme, where one has been manually designed and the other generated by HLS. the filters have been designed in CMOS 350 nm and 40 nm. the filter manually designed provides an area reduction of 8% and depending on the signal and the application, it is able to consume from 6.6 to 43 times less energy than the synchronous version. the filter produced by HLS exhibits an area reduction of 12%, and consume from 3.3 to 28 times less energy.

关键词： Event-driven circuits nonuniform sampling scheme low-power circuits High-level synthesis

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A Comprehensive Survey on Implementation of Image processing algorithms using FPGA

A Comprehensive Survey on Implementation of Image Processing...

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Recent Advances and Innovations in Engineering (ICRAIE)

作者： S Madhava Prabhu Seema Verma Middle East College Muscat Sultanate of Oman Banasthali University Rajasthan India

ISBN: (数字)9781728188676

ISBN: (纸本)9781728188683

Image processing is an unceasingly growing area with a range of applications including cryptography, medicine, video surveillance, remote sensing, and many more. Implementing sophisticated algorithms to process the large amount of data using software solutions makes the response slower, and that's where hardware implementation comes into the picture. Field Programmable Gate Arrays (FPGAs) are getting popular due to low latency, connectivity, parallel computing, and flexibility. the unique architecture of the FPGA has made it possible to use the technology for applying in many applications to have better and faster results. this paper is aiming at providing a comprehensive survey on the hardware implementations of image processing algorithms to facilitate the improvement in efficiency using FPGAs. the widely used Xilinx PYNQ is also presented in this paper as they play a major role in reducing the development time.

关键词： Technological innovation Image processing Software algorithms Video surveillance Hardware Software Field programmable gate arrays

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Data Prefetching for Heterogeneous Hadoop Cluster 5

Data Prefetching for Heterogeneous Hadoop Cluster

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5th international conference on Advanced Computing and Communication Systems (ICACCS)

作者： Vinutha, D. C. Raju, G. T. RNS Inst Technol Bengaluru Dept CSE Bengaluru India Vidyavardhaka Coll Engn Dept ISE Mysuru India Visvesraya Technol Univ Belagavi Karnataka India

ISBN: (纸本)9781538695333

: Hadoop is an open source implementation of MapReduce. Performance of Hadoop is affected by the overhead of communication during the transmission of large datasets to the computing node. In a heterogeneous cluster if a map task wants to process the data, which is not present in the local disk then the data transmission overhead occurs. To overcome this issue, Data Prefetching for Heterogeneous Hadoop cluster for resource optimization is proposed. data prefetching is used to fetch the input data in advance from the remote node to a particular computing node. Hence transmission of data occurs in parallel with data processing and the job execution time is reduced. Different MapReduce jobs are used to conduct the experiment. the results demonstrate that the time taken to transmit the data is reduced. the job execution time is reduced by 15% for the input data size greater than or equal to 2GB and performance improvement of 25% is obtained for 64MB block size.

关键词： Hadoop Data transmission MapReduce Data Prefetching Data processing

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Practicability of embarrassingly parallel computations for enormous miniature workloads over massive underutilized IoT 5

Practicability of embarrassingly parallel computations for e...

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5th IEEE international Women in Engineering (WIE) conference on Electrical and Computer Engineering (IEEE WIECON-ECE)

作者： Tiruvayipati, Sujanavan Yellasiri, Ramadevi Maturi Venkata Subba Rao MVSR Engn Coll Dept Comp Sci & Engn Hyderabad India Chaitanya Bharathi Inst Technol Dept Comp Sci & Engn Hyderabad India

ISBN: (纸本)9781728144993

the Internet of things (IoT) will grow seamlessly with advancements in data and communication technologies leading to the deploy meat of trillions of end devices. Its application starts with a simple home automation to a very large scale industrial automation system. the trend is leading towards huge data generation requiring high processing power. In the near future, computing resources might not be sufficient for handling dynamic humongous data production. As the technology advances, microcontrollers or System-on-Chips (SoCs) used for IoT end devices are becoming cheaper and more powerful. Hence, there is a requirement of effectively making use of huge number of underutilized IoT of the future by allocating additional microtasks in parallel which would solve the upcoming needs of the technological trend.

关键词： IoT parallel Computing Multi-threaded Microcontroller End-Device processing Massive Data Management

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Specialization Opportunities in Graphical Workloads 28

Specialization Opportunities in Graphical Workloads

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28th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Crawford, Lewis O'Boyle, Michael Univ Edinburgh Sch Informat Edinburgh Midlothian Scotland

ISBN: (纸本)9781728136134

Computer games are complex performance-critical graphical applications which require specialized GPU hardware. For this reason, GPU drivers often include many heuristics to help optimize throughput. Recently however, new APIs are emerging which sacrifice many heuristics for lower-level hardware control and more predictable driver behavior. this shifts the burden for many optimizations from GPU driver developers to game programmers, but also provides numerous opportunities to exploit application-specific knowledge. this paper examines different opportunities for specializing GPU code and reducing redundant data transfers. Static analysis of commercial games shows that 5-18% of GPU code is specializable by pruning dead data elements or moving portions to different graphics pipeline stages. In some games, up to 97% of the programs' data inputs of a particular type, namely uniform variables, are unused, as well as up to 62% of those in the GPU internal vertex-fragment interface. this shows potential for improving memory usage and communication overheads. In some test scenarios, removing dead uniform data can lead to 6x performance improvements. We also explore the upper limits of specialization if all dynamic inputs are constant at run-time. For instance, if uniform inputs are constant, up to 44% of instructions can be eliminated in some games, with a further 14% becoming constant-foldable at compile time. Analysis of run-time traces, reveals that 48-91% of uniform inputs are constant in real games, so values close to the upper limit may be achieved in practice.

关键词： Graphics processing units Pipelines Games Optimization Rendering (computer graphics) Transforms Hardware

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parallel graph partitioning optimization under PEGASUS DA application global state monitoring 13th

Parallel graph partitioning optimization under PEGASUS DA ap...

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13th international conference on parallel processing and Applied Mathematics, PPAM 2019

作者： Smyk, Adam Tudruj, Marek Grochal, Lukasz Polish-Japanese Academy of Information Technology 86 Koszykowa Street Warsaw02-008 Poland Institute of Computer Science Polish Academy of Sciences 5 Jana Kazimierza Street Warsaw01-248 Poland

ISBN: (纸本)9783030432287

the paper concerns the use of global application states monitoring in distributed programs for advanced graph partitioning optimization. Two strategies for the control design of advanced parallel/distributed graph partitioning algorithms are presented and discussed. In the first one, the parallel algorithm control runs on top of the ready to use basic graph partitioning functions available inside an existing graph partitioning METIS tool. the second control strategy is based on a genetic programing algorithm in which the applied basic graph partitioning primitives and the overall algorithmic parallel/distributed control can be freely designed by the user. In these strategies, the graph partitioning control is executed by processes/threads supervised by the application global states monitoring facilities provided inside a novel distributed program design framework PEGASUS DA. this framework provides system support to construct user-defined strongly consistent global application states and an API to define corresponding execution control. In particular, it concerns computing global control predicates on the constructed global states, the predicates evaluation and asynchronous execution control handling to obtain application global state-driven reactions. Based on such implementation, different features of the graph partitioning optimization strategies have been designed and tested. the experimental results have shown benefits of the new graph partitioning control methods designed with the use of the application global states monitoring. © Springer Nature Switzerland AG 2020.

关键词： Application programs

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Should PARSEC Benchmarks be More Parametric? A Case Study with Dedup 27

Should PARSEC Benchmarks be More Parametric? A Case Study wi...

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27th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Maron, Carlos A. F. Vogel, Adriano Griebler, Dalvan Fernandes, Luiz Gustavo Pontifical Catholic Univ Rio Grande do Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres de Maio Fac SETREM LARCC Tres De Maio Brazil

ISBN: (纸本)9781728116440

parallel applications of the same domain can present similar patterns of behavior and characteristics. Characterizing common application behaviors can help for understanding performance aspects in the real-world scenario. One way to better understand and evaluate applications' characteristics is by using customizable/parametric benchmarks that enable users to represent important characteristics at run-time. We observed that parameterization techniques should be better exploited in the available benchmarks, especially on stream processing domain. For instance, although widely used, the stream processing benchmarks available in PARSEC do not support the simulation and evaluation of relevant and modern characteristics. therefore, our goal is to identify the stream parallelism characteristics present in PARSEC. We also implemented a ready to use parameterization support and evaluated the application behaviors considering relevant performance metrics for stream parallelism (service time, throughput, latency). We choose Dedup to be our case study. the experimental results have shown performance improvements in our parameterization support for Dedup. Moreover, this support increased the customization space for benchmark users, which is simple to use. In the future, our solution can be potentially explored on different parallel architectures and parallel programming frameworks.

关键词： Benchmark testing parallel processing Microsoft Windows Streaming media Computer architecture Measurement throughput

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Hardware Implementation of Blind Source Separation Algorithm Using ZYBO Z7& Xilinx System Generator

Hardware Implementation of Blind Source Separation Algorithm...

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international conference on Renewable Energies for Developing Countries (REDEC)

作者： Mohcin Mekhfioui Amal Satif Omar Mouhib Rachid Elgouri Abdelkader Hadjoudja Laamari Hlou Laboratory of Electrical Engineering and Energy Systems Faculty of Science Ibn Tofail University Kenitra Morocco

ISBN: (数字)9781728155951

ISBN: (纸本)9781728155968

Blind Source Separation (BSS) is termed as the extraction of source signals from mixed data without or with little knowledge about the source signals. It is used in many fields of research such as military, medical and industry. Among the many challenges that must be overcome to apply BSS to a real system, implementation restrictions are the most difficult. Software implementations require a significant amount of overhead to make them applicable to real-time systems and have a lower maximum speed of operation than hardware implementations. When speed is desired, the algorithm should be implemented on specialized hardware such as a Field Programmable Gate Array(FPGA) which allows the user to take advantage of parallel computational abilities. this paper describes the methodology for implementing real-time DSP applications on FPGA and the concept of hardware software cosimulation of the Second Order Blind Identification (SOBI) algorithm using MATLAB Simulink and Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA ZYBO Z7 Zynq-7020.

关键词： Field programmable gate arrays Blind source separation Generators Signal processing algorithms Hardware Real-time systems Software packages

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Design of Delay Efficient Hybrid Adder for High Speed Applications 5

Design of Delay Efficient Hybrid Adder for High Speed Applic...

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5th international conference on Advanced Computing and Communication Systems (ICACCS)

作者： Nithya, J. Ramesh, S. R. Amrita Vishwa Vidyapeetham Amrita Sch Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

ISBN: (纸本)9781538695333

Complex processor system design is partitioned into smaller sub-systems. these subsystems consist of circuits such as the adder, subtractor, multiplier, and functional units. Adders are the elementary building block in these arithmetic subsystems. Arithmetical and Logical Unit (ALU) is an essential component in CPU. processing speed in CPU depends upon the time taken for processing a data. In the critical path of arithmetic subsystems, the main components are adders. the important metric for measuring the quality of adders is the critical-path delay, number of logic levels and area. Improving the speed without compromising the power is of greater concern. thus, there is a need for an energy-efficient, low-power, and high-performance architecture. In this paper, a modified approach is presented to address this issue. the design employed utilizes the advantage of parallel prefix architecture (PPA) design for low power applications. Hardware description language (HDL) is used to describe the functionality of the system. To effectively implement this adder we use the concept of "Hybrid Variable Latency" technique. the Performance parameters of the adder are reported using Cadence tool (RTL-Compiler) in 45-nm technology and functionality of the design is validated using Vivado HLS In comparison with the existing techniques, the proposed scheme is relatively faster and also it shows improvement in delay by 7.19% and 15.63% respectively.

关键词： Adders Low power parallel prefix architecture,architecture Hybrid structure Variable stage

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MIMO Detection algorithms and architectures

MIMO Detection Algorithms and Architectures

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Communication, Image and Signal processing (CCISP), international conference on

作者： Houzuo Liu School of Microelectronics Xidian University Xi’An China

ISBN: (数字)9781728185897

ISBN: (纸本)9781728185903

Massive multiple-input multiple-output (MIMO) is a novel communication technique featured with tens of users at terminals are served by hundreds of antennas at the base-station. It is a promising solution for upcoming 5G communication and has been adopted by standards such as 3GPP LTE and IEEE 802.11n In due to its higher spectral and energy efficiency. However, prohibitive computation complexity of data detection, low hardware efficiency and high hardware complexity have been the obstacle for wide application of MIMO. In this paper, a comprehensive summary about designs of algorithm and VLSI hardware architecture to solve mentioned problems will be proposed. these designs include using innovative Truncated Neumann series, Gauss-Seidel Method and so on to lower computational complexity and using iterative computation unit, pipeline design and so on to improve the hardware architecture. these methods have improved the performance of MIMO from different aspects and to different extends. Based on the summary, some improvement of mentioned methods and prediction of probable trends of the development of the technique will be articulated. All these methods and future development should be focused on finding better ways to circumvent matrix inversion and minimize deterioration in other aspects brought by it.

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