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PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 13

PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Cam...

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13th international conference on Distributed Smart Cameras (ICDSC)

作者： Carballo-Hernandez, Walther Berry, Francois Pelcat, Maxime Arias-Estrada, Miguel Inst Pascal Dept Images Percept Syst & Robot Aubiere France UMR CNRS Inst Natl Sci Appliquees INSA Rennes IETR Dept Images Rennes France INAOE Dept Comp Sci Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia (R) Jetson TX2 for the CPU-GPU side and an Intel Altera (R) Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Heterogeneous Computing Edge Computing Internet of things parallel Programming Single Instruction Multiple Data Pipelining Models of Computation and Architecture

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A Field Programmable Process-In-Memory Architecture Based on RRAM Technology

A Field Programmable Process-In-Memory Architecture Based on...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Yuan Liang Longxiang Yin Ning Xu School of Computer Science and Technology Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Engineering Wuhan University of Technology Wuhan China

Conventional reconfigurable architectures, e.g., Field-Programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： Nonvolatile memory Computer architecture Switches Routing Delays System-on-chip Reconfigurable architectures

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Analysis of relationship between SIMD-processing features used in NVIDIA GPUs and NEC SX-Aurora TSUBASA vector processors 1

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15th international conference on parallel Computing Technologies, PaCT 2019

作者： Afanasyev, Ilya V. Voevodin, Vadim V. Voevodin, Vladimir V. Komatsu, Kazuhiko Kobayashi, Hiroaki Research Computing Center of Moscow State University Moscow119234 Russia Tohoku University SendaiMiyagi980-8579 Japan

ISBN: (数字)9783030256364

ISBN: (纸本)9783030256357

this paper presents comprehensive analysis of main SIMD-processing features and computational characteristics of three high performance architectures: two NVIDIA GPU architectures (of Pascal and Volta generations) and NEC SX-Aurora TSUBASA vector processor. Since both these types of architectures strongly rely on using SIMD-processing features, certain similarities of data-processing principles can be found between them. However, despite having vectorised data-processing included in both NVIDIA GPU and NEC SX-Aurora TSUBASA architectures, vectorisation features of both architectures are implemented in completely different ways. these differences lead to several fundamental restrictions on classes of algorithms which can be efficiently implemented on corresponding platforms. this paper is devoted to the research of the possibility of porting various classes of programs and algorithms among the discussed architectures with a focus on utilising all vectorisation features available. However, without a detailed analysis of similar and different SIMD-processing features in these architectures, it is impossible to approach this problem. the performed analysis allowed us to identify several important examples of typical applications and algorithms. Some of them demonstrated comparable and the others showed different efficiency on NVIDIA GPUs and NEC SX-Aurora TSUBASA vector processors, including reduction operations, programs relying on frequent indirect memory accesses and data-transfers through co-processor interconnect. Moreover, the conducted analysis allows to easily extend this set of examples to approach the problem of automated porting of programs between the reviewed architectures, what we consider as an important direction of our future research. © 2019, Springer Nature Switzerland AG.

关键词： Graphics processing unit

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Run Time Optimization using a novel implementation of parallel-PSO for real-world applications

Run Time Optimization using a novel implementation of Parall...

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international conference on Cloud Technologies and Applications (CloudTech)

作者： Amine Chraibi Said Ben Alla Abdellah Touhafi Abdellah Ezzati Faculté Sciences et Techniques Laboratoire Veille pour les Technologies Emergentes Hassan First University of Settat Settat Morocco Vrije Universiteit Brussel Brussels Belgium

ISBN: (数字)9781728161754

ISBN: (纸本)9781728161761

the majority of optimization algorithms and methods generally necessitate a considerable run time to reach their goal. Most of them are used mainly in real-world applications. this article concentrates on an efficient and well-known algorithm to solve optimization problems: the Particle Swarm Optimisation algorithm (PSO). this algorithm needs a considerable run time to solve an optimization problem with a high dimension space and data. the article also concentrates on OpenCL, which defines a common parallel programming language for various devices such as GPU, CPU, FPGA, etc. In order to minimize the run time of PSO, this paper introduces a new implementation of PSO in OpenCL. By decomposing the PSO code into two fragments, each one can run simultaneously. the experimental results covered both the sequential and parallel implementations. Furthermore, show that the PSO' OpenCL implementation is faster than the Sequential-PSO implementation. the OpenCL profiling results show the timing of each part of the executing of PSO in OpenCL.

关键词： Cloud computing Processor scheduling Graphics processing units Timing Particle swarm optimization Optimization Field programmable gate arrays

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Multiple algorithms Against Multiple Hardware architectures: Data-Driven Exploration on Deep Convolution Neural Network 16th

Multiple Algorithms Against Multiple Hardware Architectures:...

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16th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2019

作者： Xu, Chongyang Luan, Zhongzhi Gao, Lan Wang, Rui Zhang, Han Zhang, Lianyi Liu, Yi Qian, Depei Beihang University Beijing China Science and Technology on Special System Simulation Laboratory Beijing Simulation Center Beijing China

ISBN: (纸本)9783030307080

With the rapid development of deep learning (DL), various convolution neural network (CNN) models have been developed. Moreover, to execute different DL workloads efficiently, many accelerators have been proposed. To guide the design of both CNN models and hardware architectures for a high-performance inference system, we choose five types of CNN models and test them on six processors and measure three metrics. With our experiments, we get two observations and conduct two insights for the design of CNN algorithms and hardware architectures. © 2019, IFIP international Federation for Information processing.

关键词： Neural network models

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Hardware Deceleration of Kvazaar HEVC Encoder 19th

Hardware Deceleration of Kvazaar HEVC Encoder

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19th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation (SAMOS)

作者： Sainio, Joose Mercat, Alexandre Vanne, Jarno Tampere Univ Tampere Finland

ISBN: (纸本)9783030275624;9783030275617

High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding (AVC) standard but tackling its huge complexity calls for efficient HEVC codec implementations. the recent advances in Graphics processing Units (GPUs) have made programmable general-purpose GPUs (GPGPUs) a popular option for accelerating various video coding tools. Massively parallel GPU architectures are particularly well suited for hardware-oriented full search (FS) algorithm in HEVC integer motion estimation (IME). this paper analyzes the feasibility of a GPU-accelerated FS implementation in the practical Kvazaar open-source HEVC encoder. According to our evaluations, implementing FS on AMD Radeon RX 480 GPU makes Kvazaar 12.5 times as fast as the respective anchor implemented entirely on an Intel 8-core i7 processor. However, the obtained speed gain is lost when fast IME algorithms are put into use in the anchor. For example, executing the anchor with hexagon-based search (HEXBS) algorithm is almost two times as fast as our GPU-accelerated proposal and the benefit of GPU offloading is reduced to a slight coding gain of 1.2%. Our results show that accelerating IME on a GPU speeds up non-practical encoders due to their enormous inherent complexity but the price paid with practical encoders tends to be too high. Conditional processing schemes of fast IME algorithms can be efficiently executed on processors without any substantial coding loss over that of FS. Nevertheless, we still believe there might be room for exploiting GPU on IME acceleration but GPU-parallelized fast algorithms are needed to get value for additional implementation cost and power budget.

关键词： High Efficiency Video Coding (HEVC) HEVC encoder Graphics processing Unit (GPU) Integer Motion Estimation (IME) Full-Search (FS)

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Neural Network architectures for Electricity Consumption Forecasting 12

Neural Network Architectures for Electricity Consumption For...

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IEEE Int Congr on Cybermat / 12th IEEE Int Conf on Cyber, Phys and Social Comp (CPSCom) / 15th IEEE Int Conf on Green Computing and Communications (GreenCom) / 12th IEEE Int Conf on Internet of things (ithings) / 5th IEEE Int Conf on Smart Data

作者： Heghedus, Cristina Segarra, Santiago Chakravorty, Antorweep Rong, Chunming Univ Stavanger Dept Comp Sci & Elect Engn Stavanger Norway Rice Univ Dept Elect & Comp Engn POB 1892 Houston TX 77251 USA

ISBN: (纸本)9781728129808

Advancing Data Science has become a central goal in the era of Big Data, Cloud Computing, and the Internet of things. Data science includes a multitude of methods, algorithms, and systems that are used to extract hidden patterns and knowledge from data. this paper is centered around machine learning (ML) models, and their implementation and applicability in the field of the energy informatics. Four neural networks (NNs) are proposed for computational experiments on electricity consumption forecasting. the NNs considered are back propagation neural network (BPNN), fully recurrent neural network (fRNN), long short-term memory network (LSTM), and gated recurrent unit (GRU). the four models are implemented using PyTorch, an open-source ML framework. By comparing their predictive performance, we find that LSTM and GRU attain lower errors than the other two models. More precisely, GRU presents better performance for the daily forecast whereas LSTM outperforms the rest for the monthly forecast. Insights about PyTorch are also provided, as it represents a recent addition to state of the art technologies, in terms of implementation.

关键词： PyTorch TensorFlow parallel training GPU programming Electricity consumption

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Using models of parallel specialized processors to solve the problem of signal separation 5

Using models of parallel specialized processors to solve the...

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Data Science Session at the 5th international conference on Information Technology and Nanotechnology, DS-ITNT 2019

作者： Zasov, V.A. Samara State Transport University Svobody street 2B Samara443066 Russia

this paper considers models of highly efficient specialized processors used for parallel data processing as part of solving the problem of extracting individual signals from an additive mixture of several signals. the proposed models of recursive, nonrecursive, and regularization-based parallel specialized processors provide versatility in solving the problem of signal separation with various algorithms. An advantage of regularization-based processors is that they make the solution stable under conditions where the parameters of objects exhibit expected uncertainty when the inverse problem of signal separation is ill-posed. this paper presents the results we obtained from an asymptotic analysis of the computational complexity involved. the results identify the time it takes to solve problems by using specialized processors. the paper also identifies the conditions for the efficient use of specialized processors. © 2019 CEUR Workshop Proceedings.

关键词： Inverse problems

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Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Design and Verification of High-Speed Radix-2 Butterfly FFT ...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Utsav Kumar Malviya Government Engineering College Bilaspur India

ISBN: (数字)9781728155180

ISBN: (纸本)9781728155197

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). this work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). the operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. this work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2 2 had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. this work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.

关键词： Adders Random access memory Pipeline processing conferences Market research Informatics Digital signal processing

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An OpenCL Implementation of an Image Filter on FPGA 5

An OpenCL Implementation of an Image Filter on FPGA

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5th IEEE international conference on Computer and Communications, ICCC 2019

作者： Nakasone, Seigen Ofverstedt, Lars-Goran Wilken, Gunnar Skoglund, Ulf Okinawa Institute of Science and Technology Graduate University 1919-1 Tancha Structural Cellular Biology Unit Onna-son Okinawa904-0495 Japan

ISBN: (纸本)9781728147437

FPGAs (Field-Programmable Gate Array) may offer higher performance than CPU architectures. Hardware Description Languages (HDL), such as VHDL and Verilog, which are traditionally used to program FPGAs, are known as hard to learn, to use, and to debug. Optionally, High Level Synthesis (HLS), such as OpenCL, allows developers to focus on the design of functions following a high-level software development flow, makes it easier to program FPGAs. this paper implements an image filter in the frequency domain on an FPGA board by using OpenCL, making the FPGA board an accelerator device to the host PC. the experiment results show that the filter implemented on the FPGA device can be optimized by pipelining the signal processing tasks onto the FPGA and reduce the I/O requirements between host PC and FPGA. the optimized FPGA implementation has higher performance than the image filter totally implemented on CPU. © 2019 IEEE.

关键词： Image processing

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