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An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. this is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. this hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

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A Customized processing-in-Memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. the design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

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Vectorized parallel Sparse Matrix-Vector Multiplication in PETSc Using AVX-512 18

Vectorized Parallel Sparse Matrix-Vector Multiplication in P...

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47th international conference on parallel processing (ICPP)

作者： Zhang, Hong Mills, Richard T. Rupp, Karl Smith, Barry F. Argonne Natl Lab Math & Comp Sci Div Lemont IL 60439 USA TU Wien Inst Microelect Vienna Austria

ISBN: (纸本)9781450365109

Emerging many-core CPU architectures with high degrees of single-instruction, multiple data (SIMD) parallelism promise to enable increasingly ambitious simulations based on partial differential equations (PDEs) via extreme-scale computing. However, such architectures present several challenges to their efficient use. Here, we explore the efficient implementation of sparse matrix-vector (SpMV) multiplications-a critical kernel for the workhorse iterative linear solvers used in most PDE-based simulations-on recent CPU architectures from Intel as well as the second-generation Knights Landing Intel Xeon Phi, which features many CPU cores, wide SIMD lanes, and on-package high-bandwidth memory. Traditional SpMV algorithms use compressed sparse row storage format, which is a hindrance to exploiting wide SIMD lanes. We study alternative matrix formats and present an efficient optimized SpMV kernel, based on a sliced ELLPACK representation, which we have implemented in the PETSc library. In addition, we demonstrate the benefit of using this representation to accelerate preconditioned iterative solvers in realistic PDE-based simulations in parallel.

关键词： parallel SpMV PETSc vectorization many-core Xeon Phi

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Massively parallel Skyline Computation For processing-In-Memory architectures 18

Massively Parallel Skyline Computation For Processing-In-Mem...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Zois, Vasileios Gupta, Divya Tsotras, Vassilis J. Najjar, Walid A. Roy, Jean-Francois Univ Calif Riverside Riverside CA 92521 USA UPMEM SAS Grenoble France

ISBN: (纸本)9781450359863

processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing the 'memory wall' crisis by prioritizing the integration of processors within DRAM. It promotes low data access latency, high bandwidth, massive parallelism, and low power consumption. the skyline operator is a known primitive used to identify those multi-dimensional points offering optimal trade-offs within a given dataset. For large multidimensional dataset, calculating the skyline is extensively compute and data intensive. Although, PIM systems present opportunities to mitigate this cost, their execution model relies on all processors operating in isolation with minimal data exchange. this prohibits direct application of known skyline optimizations which are inherently sequential, creating dependencies and large intermediate results that limit the maximum parallelism, throughput, and require an expensive merging phase. In this work, we address these challenges by introducing the first skyline algorithm for PIM architectures, called DSky. It is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing. Our experiments demonstrate that it outperforms the state-of-the-art algorithms for CPUs and GPUs, in most cases. DSky achieves 2x to 14x higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures. Furthermore, we showcase DSky's good scaling properties which are intertwined with PIM's ability to allocate resources with minimal added cost. In addition, we showcase an order of magnitude better energy consumption compared to CPUs and GPUs.

关键词： processing-in-memory skyline queries pareto dominance massive parallelism processing-near-memory load balancing

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Distributed image processing based on the same IP-cores in FPGA-architecture 5

Distributed image processing based on the same IP-cores in F...

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Data Science Session at the 5th international conference on Information Technology and Nanotechnology, DS-ITNT 2019

作者： Zakharov, V.M. Shalagin, S.V. Eminov, B.F. Kazan National Research Technical University named after A.N. Tupolev Karl Marks 10 Kazan420111 Russia

the problem of processing images, i. e., two-dimensional data arrays, was solved through implementing two-dimensional fast Fourier transform (FFT) when using single-type hardware modules – IP-cores in the Virtex-6 FPGA architecture. We have shown the possibility of the parallel implementation of each stage in the two-dimensional FFT, based on four "butterfly"-type transforms (BTr) over four elements of the data array being processed. Estimations were obtained regarding time- and hardware complexity of the IP-core implementing BTrs and used in implementing the one-dimensional FFT. the results obtained can be used in estimating hardware and time consumption when performing a two-dimensional FFT over an array of the pre-defined dimensionality in using existing and forthcoming distributed programmable-architecture systems. © 2019 CEUR Workshop Proceedings.

关键词： Intellectual property core

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Expediting parallel Graph Connectivity algorithms 25

Expediting Parallel Graph Connectivity Algorithms

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25th IEEE international conference on High Performance Computing, Data and Analytics (HiPC)

作者： Wadwekar, Mihir Kothapalli, Kishore Int Inst Informat Technol Hyderabad 500032 India

ISBN: (纸本)9781538683866

Finding whether a graph is k-connected, and the identification of its k-connected components is a fundamental problem in graph theory. For this reason, there have been several algorithms for this problem in both the sequential and parallel settings. Several recent sequential and parallel algorithms for k-connectivity rely on one or more breadth-first traversals of the input graph. While BFS can be made very efficient in a sequential setting, the same cannot be said in the case of parallel environments. A major factor in this difficulty is due to the inherent requirement to use a shared queue, balance work among multiple threads in every round, synchronization, and the like. Optimizing the execution of BFS on many current parallel architectures is therefore quite challenging. For this reason, it can be noticed that the time spent by the current parallel graph connectivity algorithms on BFS operations is usually a significant portion of their overall runtime. In this paper, we study how one can, in the context of algorithms for graph connectivity, mitigate the practical inefficiency of relying on BFS operations in parallel. Our technique suggests that such algorithms may not require a BFS of the input graph but actually can work with a sparse spanning subgraph of the input graph. the incorrectness introduced by not using a BFS spanning tree can then be offset by further post-processing steps on suitably defined small auxiliary graphs. Our experiments on finding the 2, and 3-connectivity of graphs on Nvidia K40c GPUs improve the state-of-the-art on the corresponding problems by a factor 2.2x, and 2.1x respectively.

关键词： Testing parallel algorithms Phase change random access memory Graphics processing units Data structures Synchronization

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Rigel: A Framework for OpenMP PerformanceTuning

Rigel: A Framework for OpenMP PerformanceTuning

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Piyumi Rameshka Pasindu Senanayake thulana Kannangara Praveen Seneviratne Sanath Jayasena tharindu Rusira Mary Hall Dept of Computer Science Engineering University of Moratuwa Katubedda Sri Lanka School of Computing University of Utah Salt Lake City UT

ISBN: (纸本)9781728120591

OpenMP allows developers to harness the power of shared memory multiprocessing in C and C++ applications, but the performance gained with OpenMP is highly sensitive to the underlying hardware, making performance portability across different hardware architectures fragile. For example, in mapping a parallel for loop to hardware, OpenMP 4 offers commands for exploiting vector instructions (simd directives) and automatic GPU offloading (target directives), as well as schedule directives for CPU load balancing. these benefits come with a cost. A developer has to be well aware of the architecture details, and the application, and must iteratively tune to determine the best combination of pragma directives delivering higher performance for the given target architecture. Hence in this paper we introduce Rigel, a framework that automates these decisions to arrive at optimized OpenMP annotated code. Given a code segment with inherent parallelism, our framework uses separate machine learning classification models to predict the anticipated benefit of each optimization. Both Vector Classification and GPU Offloading Classification models perform with average accuracies of 83%. Succeeding the classification process, code segments are optimized accordingly. Our results show that GPU offloading optimization lead to an average speedup of 8x over default non-optimized CPU parallel execution (pragma omp parallel for) and average Vector optimization speedup is 6x compared to LLVM Clang 4.0 auto-vectorization. Furthermore Scheduling mechanism selection process results in overall accuracy of 90%.

关键词： Feature extraction Graphics processing units Optimization Hardware Machine learning Tuning Computer architecture

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qLD: High-performance Computation of Linkage Disequilibrium on CPU and GPU

qLD: High-performance Computation of Linkage Disequilibrium ...

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IEEE Symposium on Bioinformatics and Bioengineering (BIBE)

作者： Charalampos theodoris Nikolaos Alachiotis Tze Meng Low Pavlos Pavlidis Technical University of Crete Greece University of Twente The Netherlands Carnegie Mellon University USA Foundation for Reseach and Technology-Hellas Greece

ISBN: (数字)9781728195742

ISBN: (纸本)9781728195759

Linkage disequilibrium (LD) is the non-random association between alleles at different loci. Assessing LD in thousands of genomes and/or millions of single-nucleotide poly-morphisms (SNPs) exhibits excessive time and memory requirements that can potentially hinder future large-scale genomic analyses. To this end, we introduce qLD (quickLD) (https//***/StrayLamb2lqLD), a highly optimized open-source software that assesses LD based on Pearson's correlation coefficient. qLD exploits the fact that the computational kernel for calculating LD can be cast in terms of dense linear algebra operations. In addition, the software employs memory-aware techniques to lower memory requirements, and parallel GPU architectures to further shorten analysis times. qLD delivers up to 5x faster processing than the current state-of-the-art software implementation when run on the same CPU, and up to 29x when computation is offloaded to a GPU. Furthermore, the software is designed to quantity allele associations between arbitrarily distant loci in a time-and memory-efficient way, thereby facilitating the evaluation of long-range LD and the detection of co-evolved genes. We showcase qLD on the analysis of 22,554 complete SARS-CoV-2 genomes.

关键词： Couplings Memory management Graphics processing units Genomics Central processing Unit Kernel Bioinformatics

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Improving Performance and Energy Efficiency of Geophysics Applications on GPU architectures 5th

Improving Performance and Energy Efficiency of Geophysics Ap...

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5th Latin American conference on High Performance Computing, CARLA 2018

作者： Pavan, Pablo J. Serpa, Matheus S. Carreño, Emmanuell Diaz Martínez, Víctor Padoin, Edson Luiz Navaux, Philippe O. A. Panetta, Jairo Mehaut, Jean-François Informatics Institute Federal University of Rio Grande do Sul – UFRGS Porto Alegre Brazil Department of Informatics Federal University of Paraná – UFPR CuritibaParaná Brazil Department of Exact Sciences and Engineering Regional University of the Northwest of the State of Rio Grande do Sul – UNIJUI Ijuí Brazil Computer Science Division Technological Institute of Aeronautics – ITA São José dos Campos Brazil Laboratoire d’Informatique de Grenoble University of Grenoble – UGA Grenoble France

ISBN: (纸本)9783030162047

Energy and performance of parallel systems are an increasing concern for new large-scale systems. Research has been developed in response to this challenge aiming the manufacture of more energy efficient systems. In this context, this paper proposes optimization methods to accelerate performance and increase energy efficiency of geophysics applications used in conjunction to algorithm and GPU memory characteristics. the optimizations we developed applied to Graphics processing Units (GPU) algorithms for stencil applications achieve a performance improvement of up to 44.65% compared with the read-only version. the computational results have shown that the combination of use read-only memory, the Z-axis internalization and reuse of specific architecture registers allow increase the energy efficiency of up to 54.11% when shared memory was used and increase of up to 44.53% when read-only was used. © Springer Nature Switzerland AG 2019.

关键词： Graphics processing unit

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Massively parallel Computation of Linear Recurrence Equations with Graphics processing Units 18

Massively Parallel Computation of Linear Recurrence Equation...

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18th international conference on Embedded Computer Systems - architectures, Modeling, and Simulation (SAMOS)

作者： Sung, Wonyong Lee, Dong-hwan Hwang, Kyuyeon Seoul Natl Univ Dept Elect Engn & Comp Sci Seoul South Korea

ISBN: (纸本)9781450364942

Graphics processing units (GPUs) show very high performance when executing many parallel programs;however their use in solving linear recurrence equations is considered difficult because of the sequential nature of the problem. Previously developed parallel algorithms, such as recursive doubling and multi-block processing, do not show high efficiency in GPUs because of poor scalability with the number of threads. In this work, we have developed a highly efficient GPU-based algorithm for recurrences using a thread-level parallel (TLP) approach, instead of conventional thread-block level parallel (TBLP) methods. the proposed TLP method executes all of the threads as independently as possible to improve the computational efficiency and employs a hierarchical structure for inter-thread communication. Not only constant but also time-varying coefficient recurrence equations are implemented on NVIDIA GTX285, GTX580 and GTX TITAN X GPUs, and the performances are compared with the results on single-core and multi-core SIMD CPU-based PCs.

关键词： Graphics processing unit (GPU) massively parallel processing linear recurrence equation prefix-sum scan

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