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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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A 90-nm CMOS Low-Energy Dual-Channel Serial/parallel Multiplier

A 90-nm CMOS Low-Energy Dual-Channel Serial/Parallel Multipl...

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Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)

作者： Dina M. Ellaithy Magdy A. El-Moursy Electronics Research Institute (ERI) Cairo Egypt Design Creation Division Mentor Graphics Siemens Business Cairo Egypt

ISBN: (数字)9781728163543

ISBN: (纸本)9781728163550

this paper presents an integrated 90-nm CMOS low-energy dual-channel multiplier based on the serial/parallel scheme. Moreover, a comparative study of different multipliers is accomplished at 90 nm CMOS technology. Due to the tendency of the market to minimize devices' size to make them portable, small implementation area is considered by using the dual-channel multiplier. In this paper, a new implementation of multiplication process comes to exceed the battery lifetime by decreasing the power consumption by up to 93%. Furthermore, there is a reduction in the area by up to 67% as compared with previous work which makes it more appropriate for low power handheld devices applications. Also, great saving in energy is attained by using the proposed scheme when performing complex multiplications task.

关键词： Hardware Clocks Signal processing algorithms Finite impulse response filters Delays CMOS technology Power demand

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parallel Communication Mechanisms in Solving Integral Equations for Electromagnetic Scattering Based on the Method of Moments 18th

Parallel Communication Mechanisms in Solving Integral Equati...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Song, Lan Peters, Dennis K. Huang, Weimin Liu, Zhiwei Lei, Lixia Wen, Tangliu Wuhan Univ Sch Comp State Key Lab Software Engn Wuhan 430072 Hubei Peoples R China East China Jiaotong Univ Sch Informat Engn Nanchang 330013 Jiangxi Peoples R China Mem Univ Fac Engn & Appl Sci Elect & Comp Engn St John NF Canada

ISBN: (纸本)9783030050511;9783030050504

In this paper, a parallel solution of impedance filling was studied to improve the efficiency for the method of moments (MOM) in solving the integral equation for electromagnetic scattering. Based on the formalization method, the correctness verification method of the parallel communication protocol was proposed to avoid the abnormal situation such as deadlock caused by unsynchronized MPI message delivery. Finally, a numerical example is given to verify the accuracy of the parallel algorithm in a multi-core cluster environment, and the parallel efficiency and computational capability are also tested. From the experiment data, it can be seen that the results of the parallel-based integral equation match well with the results of the Mie analytical solution. the parallel algorithm proposed in this paper is evaluated in terms of the acceleration ratio and parallel efficiency. the experimental results demonstrate the reliability and effectiveness of the method.

关键词： Formal verification parallel communication Electromagnetic scattering Petri net

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A Framework with Cloud Integration for CNN Acceleration on FPGA Devices 32

A Framework with Cloud Integration for CNN Acceleration on F...

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and Distributed processing Symposium (IPDPS)

作者： Raspa, Niccolo Natale, Giuseppe Bacis, Marco Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Via Ponzio 34-5 Milan Italy

ISBN: (纸本)9781538655559

the recent years have seen a rapid diffusion of deep learning algorithms as Convolutional Neural Networks (CNNs), and as a consequence, an intensification of industrial and academic research focused on optimizing their implementation. Different computing architectures have been explored, and among all of them, FPGAs seem to be a very attractive choice, since they can deliver sustained performance with high power efficiency, as CNNs can be directly mapped onto hardware, and still offer flexibility thanks to their programmability. In this paper, we present an end-to-end framework to implement CNNs using a dataflow acceleration methodology. the resulting spatial accelerator can be scaled in size if enough resources are available and can exploit both intra- and inter-layers parallelism. We integrate the proposed framework with the deep learning engine Caffe, meaning that we are able to generate the accelerator starting from a Caffe model. We also provide cloud integration of such framework, enabling users to synthesize and deploy the accelerator on the Amazon F1 instances.

关键词： Convolutional Neural Networks Dataflow architectures Cloud-based acceleration FPGA

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A parallel Branch and Bound Algorithm for the Probabilistic TSP 18th

A Parallel Branch and Bound Algorithm for the Probabilistic ...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Amar, Mohamed Abdellahi Khaznaji, Walid Bellalouna, Monia Univ Manouba Natl Sch Comp Sci CRISTAL Lab POLE GRIFT Tunis Tunisia Tunisia SESAME Univ Ariana Tunisia

ISBN: (纸本)9783030050511;9783030050504

the paper presents parallelization of exact algorithm of resolution for the Probabilistic Traveling Salesman Problem (PTSP). this algorithm allows us, first, to verify the stability of well-solvable special cases and also to optimally solve useful instances of PTSP. It again allows to perform our version of Karp partitioning algorithm, where real problems are very large-sized. the implementation of the algorithm of Karp consists in subdividing the square plan, into sub-plans. So we transform the resolution of a large size problem to the resolution of many small size sub-problems which can be exactly solved. this application can be gridified and these different sub-problems would be processed in parallel by different nodes since they are totally independent. In each sub-plan the Branch and Bound algorithm is used. In this paper we propose two parallelizations of the Branch and Bound algorithm for the resolution of the PTSP. On the one hand, the parallelization of the branches used in the exploration of the tree, on the other hand the parallelization of the algorithm associated with the notion of partitioning introduced by Karp. We perform an experimental study conducted in a multi-core environment to evaluate the performance of the proposed approach.

关键词： PTSP parallel algorithm Open MP Simulations

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Comparative Study of Distributed Deep Learning Tools on Supercomputers 18th

Comparative Study of Distributed Deep Learning Tools on Supe...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Du, Xin Kuang, Di Ye, Yan Li, Xinxin Chen, Mengqiang Du, Yunfei Wu, Weigang Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou Peoples R China Guangdong Prov Key Lab Big Data Anal & Proc Guangzhou Peoples R China Minist Educ Key Lab Machine Intelligence & Adv Comp Guangzhou Peoples R China

ISBN: (纸本)9783030050511;9783030050504

With the growth of the scale of data set and neural networks, the training time is increasing rapidly. Distributed parallel training has been proposed to accelerate deep neural network training, and most efforts are made on top of GPU clusters. this paper focuses on the performance of distributed parallel training in CPU clusters of supercomputer systems. Using resources at the supercomputer system of "Tianhe-2", we conduct extensive evaluation of the performance of popular deep learning tools, including Caffe, TensorFlow, and BigDL, and several deep neural network models are tested, including AutoEncoder, LeNet, AlexNet and ResNet. the experiment results show that Caffe performs the best in communication efficiency and scalability. BigDL is the fastest in computing speed benefiting from its optimization for CPU, but it suffers from long communication delay due to the dependency on MapReduce framework. the insights and conclusions from our evaluation provides significant reference for improving resource utility of supercomputer resources in distributed deep learning.

关键词： Distributed deep learning Tianhe-2 Speedup Performance evaluation parallel processing

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Research on Distributed Real Time Data Space SCADA Cluster for Large Power Grid 5

Research on Distributed Real Time Data Space SCADA Cluster f...

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5th international conference on Systems and Informatics (ICSAI)

作者： Wang, Hao Jin, Fenlan Gong, Zeping Xia, Hui Chen, Wei Zhao, Lin NARI Grp Corp Beijing Beijing 100192 Peoples R China

ISBN: (纸本)9781728101200

In the field of industrial automation, the traditional master/slave real-lime data processing (SCADA) system has been unable to deal with the current massive data and diversified business demands in throughput, real-time and scalability. this paper presents a decentralized real-time data space, based decentralized management SCADA cluster solutions for the treatment of object partitioning, distributed real-time data processing, dynamic data migration and decentralized real-time data management are discussed. At last, the scheme is applied to develop the system an-d verify it.

关键词： Distributed architecture data division parallel computing decentralized management

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Efficient Belief Propagation List Decoding of Polar Codes

Efficient Belief Propagation List Decoding of Polar Codes

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international conference on ASIC

作者： Yuqing Ren Weihong Xu Zaichen Zhang Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS) National Mobile Communications Research Laboratory Southeast University Nanjing China Purple Mountain Laboratories Nanjing China

As known to all, polar codes have been chosen as the control channel codes for the enhance mobile broadband (eMBB) scenario in the 3GPP RAN1. Due to its excellent performance, polar codes also have caused widespread concern in the academia and industry. In general, polar codes can be decoded by two methods: successive cancellation (SC) and belief propagation (BP) algorithms. However, compared with the series of SC algorithms, the error-correction performance of BP decoding is not satisfactory, even though it has excellent parallel throughput. Hence, this paper proposes an efficient BP list (EBPL) decoding of polar codes which can enhance the performance to the same scale of successive cancellation list (SCL) without sacrificing decoding throughput. With reasonable complexity, the proposed EBPL decoding can achieve comparable BER and FER compared to SCL in simulation results.

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the parallel Algorithm for the 2-D Discrete Wavelet Transform 9

The Parallel Algorithm for the 2-D Discrete Wavelet Transfor...

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9th international conference on Graphic and Image processing (ICGIP)

作者： Barina, David Najman, Pavel Kleparnik, Petr Kula, Michal Zemcik, Pavel Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Bozetechova 1-2 Brno Czech Republic

ISBN: (数字)9781510617421

ISBN: (纸本)9781510617421

the discrete wavelet transform can be found at the heart of many image-processing algorithms. Until now, the transform on general-purpose processors (CPUs) was mostly computed using a separable lifting scheme. As the lifting scheme consists of a small number of operations, it is preferred for processing using single-core CPUs. However, considering a parallel processing using multi-core processors, this scheme is inappropriate due to a large number of steps. On such architectures, the number of steps corresponds to the number of points that represent the exchange of data. Consequently, these points often form a performance bottleneck. Our approach appropriately rearranges calculations inside the transform, and thereby reduces the number of steps. In other words, we propose a new scheme that is friendly to parallel environments. When evaluating on multi-core CPUs, we consistently overcome the original lifting scheme. the evaluation was performed on 61-core Intel Xeon Phi and 8-core Intel Xeon processors.

关键词： Discrete wavelet transform lifting scheme multi-core processors parallel architectures

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New Multi-objectives Scheduling Strategies in Docker SwarmKit 18th

New Multi-objectives Scheduling Strategies in Docker SwarmKi...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Menouer, Tarek Cerin, Christophe Leclercq, Etienne Univ Paris 13 Sorbonne Paris Cite LIPN CNRS UMR 7030 F-93430 Villetaneuse France

ISBN: (纸本)9783030050573;9783030050566

this paper presents new multi-objectives scheduling strategies implemented in Docker SwarmKit. Docker SwarmKit is a container toolkit for orchestrating distributed systems at any scale. Currently, Docker SwarmKit has one scheduling strategy called Spread. Spread is based only on one objective to select from a set of cloud nodes, one node to execute a container. However, the containers submitted by users to be scheduled in Docker SwarmKit are configured according to multi-objectives criteria, as the number of CPUs and the memory size. To better address the multi-objectives configuration problem of containers, we introduce the concept and the implementation of new multi-objectives scheduling strategies adapted for Cloud Computing environments and implemented in Docker SwarmKit. the principle of our multi-objectives strategies consist to select a node which has a good compromise between multi-objectives criteria to execute a container. the proposed scheduling strategies are based on a combinaison of PROMEthEE and Kung multi-objectives decision algorithms in order to place containers. the implementation in Docker SwarmKit and experiments of our new strategies demonstrate the potential of our approach under different scenarios.

关键词： Systems software Scheduling and resource management Container technology Cloud computing Application of parallel and distributed algorithms

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Implementation of high speed data transfer serialized 128/130bit encoding algorithm using 90nm technology

Implementation of high speed data transfer serialized 128/13...

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international conference on Advanced Computing and Communication Systems (ICACCS)

作者： F. Mhaboobkhan M. Fathimaparveen K. Gokila P. Logapriya Department of Electronics and Communication Engineering P.A College of Engineering and Technology Coimbatore

In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a faster rate, reduces the pin counts which in turn lead to much smaller devices in an integrated circuit compared to parallel communication. Line coding can potentially help in high data transfers. In this paper 128b/130b line coding algorithm has been proposed which has the double the payload of conventional 64b/66b encoding technique, with same number of preamble bits. this increases the data transfer rate drastically. the polynomial for the scrambler has been used from IEEE clause. the proposed 128b/130b encoding algorithm has been coded using Verilog and simulated using Quartus II 9.0v .the parameters such as Setup time, Hold time, Maximum frequency, power and slack for 8b/10b, 64b/66b and 128b/130b has been compared and tabulated. the layout has been designed for 128b/130b using Cadence Encounter 14.26 tool. the comparison shows that proposed algorithm has higher data rate at the expense of increase in hardware utilization.

关键词： Encoding Registers Timing Payloads Signal processing algorithms Digital communication

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