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Performance Factor Analysis and Scope of Optimization for Big Data processing on Cluster 5

Performance Factor Analysis and Scope of Optimization for Bi...

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5th IEEE international conference on parallel, Distributed and Grid Computing (PDGC)

作者： Godara, Hanuman Govil, M. C. Pilli, E. S. NIT Sikkim Dept CSE Sikkim 737139 India MNIT Jaipur Dept CSE Jaipur Rajasthan India

ISBN: (纸本)9781728106465

Use of computational cluster for large-scale Big Data processing has attracted attention as a technology trend for its time efficiency. Modern cluster equipped with latest multi, many-core distributed shared architecture, high speed interconnect and file system, ensures high performance using message passing and multi-threading parallel approaches, also handles batch, micro-batch and stream processing of high dimensional massive dataset but running data-intensive Big Data application on compute-centric cluster imposes challenges to its performance because of several runtime overheads. In order to alleviate these bottlenecks and exploit full potential of the cluster a state of the practice, performance-oriented technical analysis covering all relevant aspects is presented in the context of Terascale Big data processing on TeraFLOPS cluster PARAM-Kanchenjunga, with identification of major factors influencing the performance or sources of these overheads related to computation, communication or IPC, memory, I/O contention, scheduling, load imbalance, synchronization, latency and network jitter;by determining their impact. As existing approaches found insufficient, to achieve possible speedup advance methods with a variety of alternatives as RDMA enabled libraries, PFS, MPI-Integrated extensions, loop tiling, hybrid parallelization are provided to consider for optimization purposes. this paper will assist to prepare performance aware design of experiments and performance modeling.

关键词： High-Performance Computing Big Data processing Computational Cluster parallelization PARAM-Kanchenjunga

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OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator 24

OuterSPACE: An Outer Product based Sparse Matrix Multiplicat...

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24th IEEE international Symposium on High Performance Computer Architecture (HPCA)

作者： Pal, Subhankar Beaumont, Jonathan Park, Dong-Hyeon Amarnath, Aporva Feng, Siying Chakrabarti, Chaitali Kim, Hun-Seok Blaauw, David Mudge, Trevor Dreslinski, Ronald Univ Michigan Ann Arbor MI 48109 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781538636596

Sparse matrices are widely used in graph and data analytics, machine learning, engineering and scientific applications. this paper describes and analyzes OuterSPACE, an accelerator targeted at applications that involve large sparse matrices. OuterSPACE is a highly-scalable, energy-efficient, reconfigurable design, consisting of massively parallel Single Program, Multiple Data (SPMD)style processing units, distributed memories, high-speed crossbars and High Bandwidth Memory (HBM). We identify redundant memory accesses to non-zeros as a key bottleneck in traditional sparse matrix-matrix multiplication algorithms. To ameliorate this, we implement an outer product based matrix multiplication technique that eliminates redundant accesses by decoupling multiplication from accumulation. We demonstrate that traditional architectures, due to limitations in their memory hierarchies and ability to harness parallelism in the algorithm, are unable to take advantage of this reduction without incurring significant overheads. OuterSPACE is designed to specifically overcome these challenges. We simulate the key components of our architecture using gem5 on a diverse set of matrices from the University of Florida's SuiteSparse collection and the Stanford Network Analysis Project and show a mean speedup of 7.9x over Intel Math Kernel Library on a Xeon CPU, 13.0x against cuSPARSE and 14.0x against CUSP when run on an NVIDIA K40 GPU, while achieving an average throughput of 2.9 GFLOPS within a 24 W power budget in an area of 87 mm2.

关键词： Sparse matrix processing application-specific hardware parallel computer architecture hardware-software codesign hardware accelerators

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16th international conference on algorithms and architectures for parallel processing - ICA3PP 2016 Collocated Workshops: 1st Workshop on Supercomputing Co-Design Technology, SCDT-2016, 1st international Workshop on theoretical Approaches to Performance Evaluation, Modeling and Simulation, TAPEMS 2016, 1st international Workshop on Trust, Security and Privacy for Big Data, BigTrust 2016, 1st edition of the workshop on Ultrascale Computing for Early Researchers, UCER 2016 and 1st international Workshop on Data Locality in Modern Computing Systems, DLMCS 2016

16th International Conference on Algorithms and Architecture...

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16th international conference on algorithms and architectures for parallel processing - ICA3PP 2016 Collocated Workshops: 1st Workshop on Supercomputing Co-Design Technology, SCDT-2016, 1st international Workshop on theoretical Approaches to Performance Evaluation, Modeling and Simulation, TAPEMS 2016, 1st international Workshop on Trust, Security and Privacy for Big Data, BigTrust 2016, 1st edition of the workshop on Ultrascale Computing for Early Researchers, UCER 2016 and 1st international Workshop on Data Locality in Modern Computing Systems, DLMCS 2016

ISBN: (纸本)9783319499550

the proceedings contain 30 papers. the special focus in this conference is on TAPEMS 2016 and BigTrust 2016. the topics include: An in-memory event tracing extension to the open trace format 2;network-aware optimization of MPDATA on homogeneous multi-core clusters with heterogeneous network;formalizing data locality in task parallel applications;improving the energy efficiency of evolutionary multi-objective algorithms;a parallel model for heterogeneous cluster;comparative analysis of OpenACC compilers;traffic sign recognition based on parameter-free detector and multi-modal representation;reversible data hiding using non-local means prediction;secure data access in hadoop using elliptic curve cryptography;statistical analysis of CCM.M-K1 international comparison based on monte carlo method;redundancy elimination in the ExaStencils code generator;a dataflow IR for memory efficient RIPL compilation to FPGAs;exploring a distributed iterative reconstructor based on split bregman using PETSc;implementation of the beamformer algorithm for the NVIDIA jetson;efficiency of GPUs for relational database engine processing;geocon;a middleware for location-aware ubiquitous applications and cellular ANTomata as engines for highly parallel pattern processing.

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Last-Position Elimination-Based parallel Learning Automata 5th

Last-Position Elimination-Based Parallel Learning Automata

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5th international conference on Communications, Signal processing, and Systems (CSPS)

作者： Huang, Yuyang Ge, Hao Huang, Jinchao Wang, Fanming Li, Shenghong Shanghai Starriver Bilingual Sch Shanghai Peoples R China Shanghai Jiao Tong Univ Dept Elect Engn Shanghai Peoples R China Riffle Inst Singapore Singapore

ISBN: (纸本)9789811032295;9789811032288

the updating scheme for Learning Automata (LA) is important. thathachar and Arvind first proposed parallel operation of leaning automata (LA), which was a promising mechanism that could maintain the accuracy while reducing convergence time. In this paper, we implement this mechanism which helps to break the limit of the convergence speed of single LA. In contrast to existing scheme, the proposed scheme eliminates the worst performed LA in the sequence of interactions, until there is only one LA left. We compare Last-Position Elimination-Based parallel Learning Automata (LEPLA) scheme with the classic one incorporating two pursuit schemes, discretized generalized pursuit algorithm (DGPA) and discretized pursuit algorithm with reward-inaction (DPRI), respectively. Simulations prove that the proposed scheme gets an evidently higher accuracy and faster convergence than the classic ones.

关键词： Artificial intelligence Learning automaton Elimination parallel

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5th international conference on Future Data and Security Engineering, FDSE 2018

5th International Conference on Future Data and Security Eng...

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5th international conference on Future Data and Security Engineering, FDSE 2018

ISBN: (纸本)9783030031916

the proceedings contain 38 papers. the special focus in this conference is on Future Data and Security Engineering. the topics include: A secure and efficient kNN classification algorithm using encrypted index search and Yao’s garbled circuit over encrypted databases;a security model for IoT networks;comprehensive study in preventive measures of data breach using thumb-sucking;intrusion prevention model for WiFi networks;security for the internet of things and the bluetooth protocol;a light-weight tightening authentication scheme for the objects’ encounters in the meetings;a privacy preserving authentication scheme in the intelligent transportation systems;Higher performance IPPC+ tree for parallel incremental frequent itemsets mining;A sample-based algorithm for visual assessment of cluster tendency (VAT) with large datasets;an efficient batch similarity processing with mapreduce;vietnamese paraphrase identification using matching duplicate phrases and similar words;automatic hyper-parameters tuning for local support vector machines;detection of the primary user’s behavior for the intervention of the secondary user using machine learning;text-dependent speaker recognition system based on speaking frequency characteristics;Static PE malware detection using gradient boosting decision trees algorithm;comparative study on different approaches in optimizing threshold for music auto-tagging;using machine learning for news verification;a short review on deep learning for entity recognition;an analysis of software bug reports using random forest;motorbike detection in urban environment;comprehensive review of classification algorithms for medical information system;new method of medical incomplete information system optimization based on action queries;Cloud media DJ platform: Functional perspective;Cloud media DJ platform: Performance perspective.

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Performance Comparison of Graph BFS Implemented in MapReduce and PGAS Programming Models 12th

Performance Comparison of Graph BFS Implemented in MapReduce...

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12th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Ryczkowska, Magdalena Nowicki, Marek Univ Warsaw Interdisciplinary Ctr Math & Computat Modeling Pawinskiego 5a PL-02106 Warsaw Poland Nicolaus Copernicus Univ Fac Math & Comp Sci Chopina 12-18 PL-87100 Torun Poland

ISBN: (纸本)9783319780542;9783319780535

Computations based on graphs are very common problems but complexity, increasing size of analyzed graphs and a huge amount of communication make this analysis a challenging task. In this paper, we present a comparison of two parallel BFS (Breath- First Search) implementations: MapReduce run on Hadoop infrastructure and in PGAS (Partitioned Global Address Space) model. the latter implementation has been developed with the help of the PCJ (parallel Computations in Java) - a library for parallel and distributed computations in Java. Both implementations realize the level synchronous strategy - Hadoop algorithm assumes iterative MapReduce jobs, whereas PCJ uses explicit synchronization after each level. the scalability of both solutions is similar. However, the PCJ implementation is much faster (about 100 times) than the MapReduce Hadoop solution.

关键词： High performance computing Hadoop MapReduce PGAS parallel and distributed computation Performance evaluation parallel graph algorithms Java

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Efficient Cross Section Reconstruction on Modern Multi and Many Core architectures 12th

Efficient Cross Section Reconstruction on Modern Multi and M...

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12th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Wang, Yunsong Hugot, Francois-Xavier Brun, Emeric Malvagi, Fausto Calvin, Christophe Univ Paris Saclay Univ Paris Sud CNRS CEAUVSQMaison Simulat F-91191 Gif Sur Yvette France Univ Paris Saclay CEA Saclay SERMA DENCEA F-91191 Gif Sur Yvette France

ISBN: (纸本)9783319780245;9783319780238

the classical Monte Carlo (MC) neutron transport employs energy lookup on long tables to compute the cross sections needed for the simulation. this process has been identified as an important performance hotspot of MC simulations, because poor cache utilization caused by random access patterns and large memory footprint makes it unfriendly to modern architectures. A former study [1] shows that such method presents little vectorization potential in a real-case simulation due to the memory-bound nature. In this paper, we revisit a cross section reconstruction method introduced by Hwang [2] to evaluate another solution. the reconstruction converts the problem from memory-bound to compute-bound. Only several variables for each resonance are required instead of the conventional pointwise table covering the entire resolved resonance region. though the memory space is largely reduced, this method is really time-consuming. After a series of optimizations, results show that the reconstruction kernel benefits well from vectorization and can achieve 1806 GFLOPS (single precision) on a Knights Landing 7250, which represents 67% of its effective peak performance.

关键词： Monte Carlo Neutron transport Cross section On-the-fly reconstruction Vectorization Intel MIC

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Radix Tree for Binary Sequences on GPU 12th

Radix Tree for Binary Sequences on GPU

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12th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Kaczmarski, Krzysztof Wolant, Albert Warsaw Univ Technol Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (纸本)9783319780245;9783319780238

In this paper, we present radix tree index structure (R-Trie) able to perform lookup over a set of keys of arbitrary length optimized for GPU processors. We present a fully parallel SIMD organized creation and search strategies. the R-Trie supports configurable bit stride for each level and nodes statistics for optimization purposes. We evaluate the performance using two search strategies and Longest Prefix Match (LPM) problem for computer networks. Unlike dedicated LPM algorithms we do not incorporate knowledge about the data or the network masks statistics into the tree construction or algorithm behavior. Our solution may be used in general purpose indexing structures where a batch search of massive number of keys is needed. (the research was funded by National Science Center, decision DEC-2012/07/D/ST6/02483.)

关键词： Radix tree parallel search Longest prefix match GPU

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2018 IEEE international conference on Consumer Electronics-Taiwan, ICCE-TW 2018

2018 IEEE International Conference on Consumer Electronics-T...

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5th IEEE international conference on Consumer Electronics-Taiwan, ICCE-TW 2018

ISBN: (纸本)9781538663011

the proceedings contain 255 papers. the topics discussed include: an experimental study of harvesting channel state information of WiFi signals;area-efficient VLSI architecture of high-order matched filter design using odd-and-even phase processing for image recognition applications;a concept proposal for peer- to-peer power exchange by market mechanism;behavior analysis of flooding attacks in sparse mobile ad-hoc networks;a parallel-SSHI rectifier for piezoelectric energy harvesting;detection of focal asymmetry based on pair of mammographic images;stable time reduction by LD-O in PWM switching buck converter;and an energy harvester circuit with clock booster for piezoelectric energy harvesting.

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Dynamic Hand Gesture Recognition Based on parallel HMM Using Wireless Signals 5th

Dynamic Hand Gesture Recognition Based on Parallel HMM Using...

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5th international conference on Communications, Signal processing, and Systems (CSPS)

作者： Xu, Jiabin Jiang, Ting Beijing Univ Posts & Telecommun Key Lab Universal Wireless Commun Beijing Peoples R China

ISBN: (纸本)9789811032295;9789811032288

Dynamic hand gesture recognition plays an important role in human computer Interaction. this paper proposes a novel method for dynamic hand gesture recognition using wireless signals. through the analysis of wireless frame structure, the preamble's signal of 802.11a is collected through Software Defined Radio platform and reserved as the data source. In addition, more than one time-domain feature sequences perform unique shape for different dynamic hand gesture. these sequences are split into single cycle (time-series) and the unavoidable electronic interference is reduced through discrete wavelet transform. At the same time, due to fuzziness of dynamic hand gesture, the amplitude and duration for the same dynamic hand gesture are not exactly same. therefore, the parallel HMM models which represent for different hand gestures and features are built for recognition. the result shows that the average recognition rate is about 90.5% for dynamic hand gesture recognition.

关键词： Dynamic gesture recognition Software defined radio Time-series parallel HMM models Wireless signals

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