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检索条件"任意字段=5th International Symposium on Code Generation and Optimization"

共 251 条记录，以下是11-20 订阅

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Decoding of QR codes Printed on Spheres 5

Decoding of QR Codes Printed on Spheres

引用

5th international symposium on Next-generation Electronics (ISNE)

作者： Lay, Kuen-Tsair Wang, Lee-Jyi Han, Pei-Lun Natl Taiwan Univ Sci & Technol Dept Elect & Comp Engn Taipei Taiwan

In this paper, we deal with the situation wherein QR codes are printed on spheres. When an image is obtained from such a QR code, it can be seriously distorted. A scheme based on conic segmentation (CS) is proposed to... 详细信息

ISBN: (纸本)9781509024391

关键词： QR code sphere conic segmentation

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Microarchitecture sensitive empirical models for compiler optimizations 07

Microarchitecture sensitive empirical models for compiler op...

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5th international symposium on code generation and optimization

作者： Vaswani, Kapil thazhuthaveetil, Matthew J. Srikant, Y. N. Joseph, P. J. Indian Inst Sci Bangalore Karnataka India Freescale Bangalore Karnataka India

ISBN: (纸本)9780769527642

this paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. the models we build relate program performance to settings of compiler optimization flags, associated heuristics and key microarchitectural parameters. Unlike traditional analytical modeling methods, this relationship is learned entirely from data obtained by measuring performance at a small number of carefully selected compiler/microarchitecture configurations. We evaluate three different learning techniques in this context viz. linear regression, adaptive regression splines and radial basis function networks. We use the generated models to a) predict program performance at arbitrary compiler/microarchitecture configurations, b) quantify the significance of complex interactions between optimizations and the microarchitecture, and c) efficiently search for 'optimal' settings of optimization flags and heuristics for any given microarchitectural configuration. Our evaluation using benchmarks from the SPEC CPU2000 suits suggests that accurate models (< 5% average error in prediction) can be generated using a reasonable number of simulations. We also find that using compiler settings prescribed by a model-based search can improve program performance by as much as 19% (with an average of 9.5%) over highly optimized binaries.

关键词： Microarchitecture Optimizing compilers Predictive models Hardware Program processors Analytical models Design optimization Performance analysis Prefetching Buildings

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Structure layout optimization for multithreaded programs 07

Structure layout optimization for multithreaded programs

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5th international symposium on code generation and optimization

作者： Raman, Easwaran Hundt, Robert Mannarswamy, Sandya Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Hewlett Packard Corp Java Compilers & Tools Lab Palo Alto CA 94303 USA

ISBN: (纸本)9780769527642

Structure layout optimizations seek to improve runtime performance by improving data locality and reuse. the structure layout heuristics for single-threaded benchmarks differ from those for multi-threaded applications running on multiprocessor machines, where the effects of false sharing need to be taken into account. In this paper we propose a technique for structure layout transformations for multi-threaded applications that optimizes both for improved spatial locality and reduced false sharing, simultaneously. We develop a semi-automatic tool that produces actual structure layouts for multi-threaded programs and outputs the key factors contributing to the layout decisions. We apply this tool on the HP-UX kernel and demonstrate the effects of these transformations for a variety of already highly hand-tuned key structures with different set of properties. We show that naive heuristics can result in massive performance degradations on such a highly tuned application, while our technique generally avoids those pitfalls. the improved structures produced by our tool improve performance by up to 3.2% over a highly tuned baseline.

关键词： Optimizing compilers Protocols Computer science Java Program processors Laboratories Runtime Application software Kernel Degradation

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Evaluating heuristic optimization phase order search algorithms

Evaluating heuristic optimization phase order search algorit...

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5th international symposium on code generation and optimization

作者： Kulkarni, Prasad A. Whalley, David B. Tyson, Gary S. Davidson, Jack W. Florida State Univ Dept Comp Sci Tallahassee FL 32306 USA Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9780769527642

Program-specific or function-specific optimization phase sequences are universally accepted to achieve better overall performance than any fixed optimization phase ordering. A number of heuristic phase order space search algorithms have been devised to find customized phase orderings achieving high performance for each function. However to make this approach of iterative compilation more widely accepted and deployed in mainstream compilers, it is essential to modi existing algorithms, or develop new ones that find near-optimal solutions quickly. As a step in this direction, in this paper we attempt to identify and understand the important properties of some commonly employed heuristic search methods by using information collected during an exhaustive exploration of the phase order search space. We compare the performance obtained by each algorithm with all others, as well as with the optimal phase ordering performance. Finally, we show how we can use the features of the phase order space to improve existing algorithms as well as devise new, and better performing search algorithms.

关键词： Search engines

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Embedded-DSL-like code generation and optimization of Bayesian Estimation Routines with User-Defined Source-to-source code Transformation Framework Xevolver 5

Embedded-DSL-like Code Generation and Optimization of Bayesi...

引用

5th international symposium on Computing and Networking (CANDAR)

作者： Suda, Reiji Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781538620878

Xevolver is a source-to-source code transformation framework where users can define their own code transformation rules. the transformations in Xevolver can break the semantics of the code, that is, the resulting code can do different computations than the original source code does. this feature of Xevolver enables its usage as a code generator like embedded DSL (Domain Specific Language). this paper demonstrates such a usage in a code generator that inputs hierarchical Bayesian models in a form of Fortran code, and outputs a code that estimates Bayesian parameters from observed data. We found that Xevolver is also useful to optimize the generated codes.

关键词： code generation Bayesian estimation code transformation code optimization

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Persistent code caching: Exploiting code reuse across executions and applications 07

Persistent code caching: Exploiting code reuse across execut...

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5th international symposium on code generation and optimization

作者： Connors, Dan Reddi, Vijay Janapa Cohn, Robert Smith, Michael D. Univ Colorado Boulder CO 80309 USA Harvard Univ Cambridge MA 02138 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9780769527642

Run-time compilation systems are challenged with the task of translating a program's instruction stream while maintaining low overhead. While software managed code caches are utilized to amortize translation costs, they are in-effective for programs with short run times or large amounts of cold code. Such program characteristics are prevalent in real-life computing environments, ranging from Graphical User Interface (GUI) programs to large-scale applications such as database management systems. Persistent code caching addresses these issues. It is described and evaluated in an industry-strength dynamic binary instrumentation system - Pin. the proposed approach improves the intra-execution model of code reuse by storing and reusing translations across executions, thereby achieving inter-execution persistence. Dynamically linked programs leverage inter-application persistence by using persistent translations of library code generated by other programs. New translations discovered across executions are automatically accumulated into the persistent code caches, thereby improving performance over time. Inter-execution persistence improves the performance of GUI applications by nearly 90%, while inter-application persistence achieves a 59% improvement. In more specialized uses, the SPEC2K INT benchmark suite experiences a 26% improvement under dynamic binary instrumentation. Finally, a 400% speedup is achieved in translating the Oracle database in a regression testing environment.

关键词： Graphical user interfaces Instruments Virtual manufacturing Costs Databases Application software Libraries Runtime Computer interfaces Testing

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code generation and optimization for transactional memory constructs in an unmanaged language

Code generation and optimization for transactional memory co...

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5th international symposium on code generation and optimization

作者： Wang, Cheng Chen, Wei-Yu Wu, Youfeng Saha, Bratin Adl-Tabatabai, Ali-Reza Intel Corp Programming Syst Lab Microprocessor Technol Labs 2200 Mission Coll Blvd Santa Clara CA 95053 USA Univ Calif Berkeley Div Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9780769527642

Transactional memory offers significant advantages for concurrency control compared to locks. this paper presents the design and implementation of transactional memory constructs in an unmanaged language. Unmanaged languages pose a unique set of challenges to transactional memory constructs - for example, lack of type and memory safety, use of function pointers, aliasing of local variables, and others. this paper describes novel compiler and runtime mechanisms that address these challenges and optimize the performance of transactions in an unmanaged environment. We have implemented these mechanisms in a production-quality C compiler and a high-performance software transactional memory runtime. We measure the effectiveness of these optimizations and compare the performance of lock-based versus transaction-based programming on a set of concurrent data structures and the SPLASH-2 benchmark suite. On a 16 processor SMP system, the transaction-based version of the SPLASH-2 benchmarks scales much better than the coarse-grain locking version and performs comparably to the fine-grain locking version. Compiler optimizations significantly reduce the overheads of transactional memory so that, on a single thread, the transaction-based version incurs only about 6.4% overhead compared to the lock-based version for the SPLASH-2 benchmark suite. thus, our system is the first to demonstrate that transactions integrate well with an unmanaged language, and can perform as well as fine-grain locking while providing the programming ease of coarse-grain locking even on an unmanaged environment.

关键词： Automatic programming

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optimization of Binary LDPC codes for the q-ary Symmetric Channel with Moderate q

Optimization of Binary LDPC Codes for the <i>q</i>-ary Symme...

引用

5th international symposium on Turbo codes and Related Topics

作者： Lechner, Gottfried Weidmann, Claudio Telecommun Res Ctr Vienna ftw A-1220 Vienna Austria

ISBN: (纸本)9781424428625

We study the optimization of binary LDPC codes for the q-ary symmetric channel with moderate alphabet sizes q. For q = 2(m), a coding scheme can be viewed as a front-end mapping q-ary symbols to groups of m bits connected to a binary code. We derive a factor graph representation of the front-end and show that it can be processed with a complexity linear in m, the number of bits per symbol. We perform an extrinsic information transfer chart analysis and use it for code optimization.

关键词： codes (symbols)

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Run-time support for optimizations based on escape analysis 07

Run-time support for optimizations based on escape analysis

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5th international symposium on code generation and optimization

作者： Kotzmann, thomas Moessenboeck, Hanspeter Johannes Kepler Univ Linz Inst Syst Software Christian Doppler Lab Automated Software Engn A-4040 Linz Austria

ISBN: (纸本)9780769527642

the Java (TM) programming language does not allow the programmer to influence memory management. An object is usually allocated on the heap and deallocated by the garbage collector when it is not referenced any longer Under certain conditions, the virtual machine can allocate objects on the stack or eliminate their allocation via scalar replacement. However even if the dynamic compiler guarantees that the conditions are fulfilled, the optimizations require support by the run-time environment. We implemented a new escape analysis algorithm for Sun Microsystems' Java HotSpot (TM) VM. the results are used to replace objects with scalar variables, to allocate objects on the stack, and to remove synchronization. this paper deals with the representation of optimized objects in the debugging information and with reallocation and garbage collection support for a safe execution of optimized methods. Assignments to fields of parameters that can refer to both stack and heap objects are associated with an extended write barrier which skips card marking for stack objects. the traversal of objects during garbage collection uses a wrapper that abstracts from stack objects and presents their pointer fields as root pointers to the garbage collector. When a previously compiled and currently executing method must be continued in the interpreter because dynamic class loading invalidates the machine code, execution is suspended and compiler optimizations are undone. Scalar-replaced objects are reallocated on the heap lazily when control returns to the invalidated method, whereas stack-allocated objects must be reallocated immediately before program execution resumes. After reallocation, objects for which synchronization was removed are relocked.

关键词： Optimizing compilers Java Runtime environment Virtual machining Dynamic compiler Algorithm design and analysis Virtual manufacturing optimization methods Debugging Sun

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AN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs 2020

AN5D: Automated Stencil Framework for High-Degree Temporal B...

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18th ACM/IEEE international symposium on code generation and optimization (CGO)

作者： Matsumura, Kazuaki Zohouri, Hamid Reza Wahib, Mohamed Endo, Toshio Matsuoka, Satoshi Barcelona Supercomp Ctr Barcelona Spain Edgecortix Inc Tokyo Japan AIST Tokyo Japan Tokyo Inst Technol Tokyo Japan RIKEN CCS Kobe Hyogo Japan RWBC OIL Tokyo Japan

ISBN: (纸本)9781450370479

Stencil computation is one of the most widely-used compute patterns in high performance computing applications. Spatial and temporal blocking have been proposed to overcome the memory-bound nature of this type of computation by moving memory pressure from external memory to on-chip memory on GPUs. However, correctly implementing those optimizations while considering the complexity of the architecture and memory hierarchy of GPUs to achieve high performance is difficult. We propose AN5D, an automated stencil framework which is capable of automatically transforming and optimizing stencil patterns in a given C source code, and generating corresponding CUDA code. Parameter tuning in our framework is guided by our performance model. Our novel optimization strategy reduces shared memory and register pressure in comparison to existing implementations, allowing performance scaling up to a temporal blocking degree of 10. We achieve the highest performance reported so far for all evaluated stencil benchmarks on the state-of-the-art Tesla V100 GPU.

关键词： Stencil Computation GPU Automatic code generation Temporal Blocking

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