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Signal processing at 250 MHz using high-performance FPGA's 97

Signal processing at 250 MHz using high-performance FPGA's

引用

Proceedings of the 1997 ACM 5th international symposium on Field-Programmable Gate Arrays, FPGA

作者： Von Herzen, Brian Rapid Prototypes Inc Carson City NV United States

ISBN: (纸本)9780897918015

this paper describes an application in high-performance signal processing using reconfigurable computing engines. the application is a 250 MHz cross-correlator for radio astronomy and was developed using the fastest available Xilinx FPGA's. We will report experimental results on the operation of CMOS FPGA's at 250 MHz, and describe the architectural innovations required to build a 250 MHz reconfigurable signal processor. Extensions of the technique to a variety of high-performance real-time signal processing algorithms are discussed. the results of this design work provide important clues as to how to improve FPGA architectures to better support real-time signal processing at hundreds of MHz. In particular, direct routing resources between logic elements are critical to preserving high performance. these routing resources need to be symmetric in order to allow for two-way communications between logic elements. Four-way symmetry and regularity would allow for orthogonal transformations of processing elements in a hierarchical fashion. Finally, experimental results indicate that clock buffering is frequently the cause of ultimate failure in speed and performance tests. Wave pipelining techniques may be suitable in clock distribution to improve performance to match that of other elements in the system.

关键词： parallel processing systems

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An efficient technique for deadlock analysis of large scale process networks 4th

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4th international symposium of Formal Methods Europe, FME 1997

作者： Martin, J.M.R Jassim, S.A. Oxford University Computing Services 13 Banbury Road Oxford0X2 6NN United Kingdom Department of Mathematics Statistics and Computer Science University of Buckingham MK18 lEG United Kingdom

ISBN: (纸本)3540635335

Nowadays we are becoming increasingly dependent on parallel or distributed computer systems for many safety critical applications. therefore, in order to avoid software precipitated catastrophes, we must look for ways to enable software engineers to design systems that are free from pathological problems such as deadlock. Traditionally deadlock has been one of the most feared problems in parallel computing. Existing tools which perform deadlock analysis can usually cope only with rather small networks due to the problem of exponential state explosion. Here we describe the implementation of a new, highly efficient, graph-theoretical approach to automatically proving deadlock-freedom which can be used to analyse CSP networks of arbitrary size. Our methods exploit previous work by S. D. Brookes, A. W. Roscoe and N. Dathi. © Springer-Verlag Berlin Heidelberg 1997.

关键词： distributed computer systems

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Model-integrated development of complex applications 5

Model-integrated development of complex applications

引用

5th international symposium on Assessment of Software Tools and Technologies

作者： Misra, A Karsai, G Sztipanovits, J Department of Electrical and Computer Engineering Vanderbilt University P.O. Box 1824 Station B Nashville 37235 TN United States

ISBN: (纸本)0818679417

Many large distributed applications are tightly integrated with their physical environments and must be adapted when their environment changes. Typically, software development methodologies do not place a large emphasis on modeling the system's environment, and hence environmental changes may lead to significant discrepancies in the software. fn this paper we argue that (1) the modeling of the environment should be an integral part of the process, and (2) to support software evolution, wherever possible, the software should be automatically generated. We present a model-integrated development approach that is capable of supporting cast effective system evolution in accordance with changes in the system's environment. the approach is supported by a ''meta-architecture'' that provides a framework for building complex software systems using COTS and custom developed software components. this framework has been successfully used in various projects. One of these projects, a site production flow visualization system far a large manufacturing operation, will be analyzed in detail. First, toe show how the model-integrated process can be generalized and used to build families of model-integrated tools that support the development of specific systems. Next, we describe how the generic architecture was customized for the particular domain. Next, we discuss how specific components were implemented and present a detailed experience report (both from developers and end-users).

关键词： model-integrated computing end-user programming component-based software integration

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parallel global routing algorithms for standard cells

Parallel global routing algorithms for standard cells

引用

international symposium on parallel Processing

作者： Z. Xing J. Chandy P. Banerjee Computer and Systems Research Laboratory University of Illinois Urbana IL USA Cadence Design Systems Chelmsford MA USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

In this paper, we propose three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC. the parallel algorithms have been implemented by using the Message Passing Interface (MPI), and have been evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon. Our experimental results show good speedups and qualities from two of these parallel algorithms. We have been able to reduce runtimes of some circuits from half an hour to 5 minutes, obtained speedups of about 4.0 to 5.0 on 8 processors, with less than 2-3% degradation of quality of the solutions.

关键词： Routing parallel algorithms distributed computing Message passing Pins Wire Contracts Concurrent computing Laboratories Sun

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Toward a scalable design for command and control systems

Toward a scalable design for command and control systems

引用

Workshop on parallel and distributed Real-Time Systems

作者： J.A. Caruso Computer Science Corporation Dahlgren VA USA

Command and control systems exist in a world of constantly shifting demands and expectations; therefore, producing scalable, evolvable systems has always been a priority of system designers. However the need to meet performance requirements has often been a restraint on scalability goals. Advances in the speed and capacity of computational and communications equipment have substantially increased the range of scalability that can be achieved while still meeting performance requirements. the High Performance distributed computing Program (HiPer-D) has demonstrated a design for the AEGIS weapons system, which is close to achieving the full range of operational requirements while providing scalability along several dimensions. this paper discusses the HiPer-D design, its context, development, and efforts to achieve system level performance.

关键词： Command and control systems Scalability Fault tolerance Hardware Communication equipment distributed computing Weapons Application software Computer architecture Resource management

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the wobbly logic engine: Proving hardness of non-rigid geometric graph representation problems 5th

引用

5th international symposium on Graph Drawing, GD 1997

作者： Fekete, Sándor P. Houle, Michael E. Whitesides, Sue Center for Parallel Computing Universität zu Köln KölnD-50923 Germany Department of Computer Science University of Newcastlc CallaghanNSW2308 Australia School of Computer Science McGill University 3480 University St. #318 MontréalQuébec Canada

ISBN: (纸本)9783540639381

the logic engine technique has been used in the past to establish the NP-hardness of a number of graph representations. the original technique can only be applied in those situations in which subgraphs exist for which the only possible layouts are rigid. In this paper we introduce an extension called the wobbly logic engine which can be used to prove the NP-hardness of several graph representations for which no such rigid layouts exist, representations by visibility and intersection in particular. We illustrate the method by using the wobbly technique to show the NP-hardness of deciding whether a graph has a nondegenerate z-axis parallel visibility representation (ZPR) by unit squares. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Visibility

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A parallel hardware evolvable computer POLYP

A parallel hardware evolvable computer POLYP

引用

Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： U. Tangen L. Schulte J.S. McCaskill Institute for Molekulare Biotechnologie Jena Germany

Previous work (J.S. McCaskill et al., 1996; 1997) has shown the power of massively parallel configurable hardware (NGEN) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom circuit simulation of fine grained physical processes via a massively parallel architecture, e.g. 144 hardware configurable field programmable gate arrays (FPGAs, XC4008, Xilinx). NGEN is optimized to implement dataflow architectures and systolic algorithms for large problems and is confectioned with high speed distributed SRAM, 144*8*256 kBit, 15ns access time, on the chip to chip interconnect. Microconfigurable FPGAs allow a further step to close the gap between micro electronics and biology on the information processing area. A design for a massively parallel microconfigurable computer (POLYP) is presented. It is designed to allow online evolution in hardware with significant locally controllable memory resources. It is also designed for high throughput dataflow applications with large problem size. Additionally, an evolvable interface between high rate measurement devices is provided to allow adaptive processing coupled with real time experimental environments. the computer represents the next logical step towards evolvable hardware interacting with biology beyond the massively parallel computer NGEN.

关键词： Hardware Concurrent computing Field programmable gate arrays Biology computing Computer architecture Circuit simulation Evolution (biology) Computational modeling Physics computing parallel architectures

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A transaction-based temporal data model for real-time databases

A transaction-based temporal data model for real-time databa...

引用

Workshop on parallel and distributed Real-Time Systems

作者： M.P. Bodlaender P.D.V. v.d. Stok S.H. Son Department of Computing Science Technical University Eindhoven Netherlands Department of Computer Science University of Virginia USA

We propose a real-time database model that deals with the temporal nature of data. Previous models assigned validity intervals with data items. A value of a data item is then only valid within the corresponding interval. In the new model, it is recognized that validity depends on the usage of the data item, therefore temporal validity is a characteristic of transactions, rather than of data items. the paper shows the influence of this different modeling on the expressiveness of the specification. It compares the transaction-based model with existing models that cover the same area, by looking at implementations that are based on these models.

关键词： Data models Transaction databases Real time systems USA Councils Character recognition Database systems

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Automated target recognition on SPLASH 2

Automated target recognition on SPLASH 2

引用

Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： M. Rencher B.L. Hutchings Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

Automated target recognition is an application area that requires special-purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high level of performance for ATR systems if the implementation can be adapted to the limited FPGA and routing resources of these architectures. the paper discusses a mapping experiment where a linear-systolic implementation of an ATR algorithm is mapped to the SPLASH 2 platform. Simple column oriented processors were used throughout the design to achieve high performance with limited nearest neighbor communication. the distributed SPLASH 2 memories are also exploited to achieve a high degree of parallelism. the resulting design is scalable and can be spread across multiple SPLASH 2 boards with a linear increase in performance.

关键词： Target recognition Field programmable gate arrays Focusing Hardware Superluminescent diodes Partitioning algorithms Synthetic aperture radar Application software Routing parallel processing

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Platform-independent verification of real-time programs

Platform-independent verification of real-time programs

引用

Workshop on parallel and distributed Real-Time Systems

作者： J. Hooman O. Van Roosmalen Department of Computing Science Eindhovan University of Technology Eindhoven Netherlands

To include the specification of timing properties in distributed programs, we propose a method to extend existing programming languages with timing annotations. these annotations provide a similar abstraction from the execution platform as is normal for non-real-time languages. Hence they enable the construction of (hard) real-time programs which can be proved correct independently of any underlying execution platform. the realization of programs on a particular platform is considered as a separate phase where, e.g., scheduling is important. We illustrate the method by means of a simple programming language which is extended with timing annotations. A formal, axiomatic, semantics of the language constructs is defined. It is used to prove the correctness of a small example program.

关键词： Timing Computer languages Object oriented programming Operating systems Real time systems Control systems Multitasking Functional programming

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