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5th IEEE international symposium on Object-Oriented Real-Time distributed Computing (ISORC 2002)

作者： Kim, KHK Im, C Athreya, P Univ Calif Irvine Irvine CA 92717 USA

ISBN: (纸本)0769515584

A key challenge in keeping distributed clocks well synchronized in a LAN environment via OS- or middleware-level mechanisms is to create an interference-free condition in a network channel(s) and a nonpreemptible on-alert condition in the responsible thread in each node during each resynchronization round while keeping the length of each round as short as possible. An approach for meeting this challenge which is based on the middleware architecture TMOSM, has been presented. A prototype implementation and its measurements indicated that with a typical network of PCs connected via a 10 Mbps Ethernet, the PC nodes can be kept synchronized within the deviation bound of 0.5 milliseconds. the organizing principle is believed to be applicable to many real-time OSs or middleware used to support distributed computing applications.

关键词： real time clock synchronization deviation embedded TMO time triggered message object middleware distributed parallel programming

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Stream oriented modular architecture with polymorphic processing engines 26

Stream oriented modular architecture with polymorphic proces...

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26th IEEE international symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014

作者： Gorobets, Andriy Pratas, Frederico Roma, Nuno Tomís, Pedro INESC-ID IST Universidade de Lisboa Portugal

ISBN: (纸本)9781479970148

Stream computing has shown to be an effective technique to decouple communication from computation in many application domains. It provides an efficient mitigation of bandwidth restrictions, by reducing the amount of memory accesses and by maximizing the available computational resources, potentiating the parallel processing using multiple execution engines. However, it frequently implies significant development costs, since efficient stream-based architectures are usually attained through application-specific full-custom processors, often tightened to the application at hand. To circumvent this limitation, a modular stream computing architecture aiming generic and high performance applications is presented. the proposed architecture, designed for reconfigurable hardware, is composed of modular processing engines that can be customized by the end-user in many ways, such as in terms of their number, type and precision of the functional units. Furthermore, these processing engines are designed as programmable cores, allowing the execution of a wide set of applications using the same configuration. From the conducted evaluation by using a series of benchmark case studies, it was observed that the proposed architecture achieves competitive results when compared with alternative solutions. © 2014 IEEE.

关键词： Engines

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Video processing on GPU: Analysis of data transfer overhead 26

Video processing on GPU: Analysis of data transfer overhead

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26th IEEE international symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014

作者： Prata, Renan Bentes, Cristiana Farias, Ricardo Department of System Engineering State University of Rio de Janeiro Rio de Janeiro RJ20550-900 Brazil COPPE/Systems Engineering Federal University of Rio de Janeiro Rio de Janeiro RJ21945-970 Brazil

ISBN: (纸本)9781479970148

In this work, we study one of the major problems in exploring the power of GPUs to accelerate video processing applications: countless frames have to be transferred back and forth between the CPU and GPU. We evaluate four different data transfer approaches currently available on modern GPUs: Standard Allocation, Pinned Memory, Data Stream, and Zero-Copy. Our results show that Data Stream is the most efficient strategy, but requires more programming effort. Zero-Copy, on the other hand, demonstrates inferior performance due to the significant latency incurred by the PCIe bus transfers for every memory access. © 2014 IEEE.

关键词： Graphics processing unit

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Accelerating DNA Sequence Analysis using Intel® Xeon Phi™ 14

Accelerating DNA Sequence Analysis using Intel® Xeon Phi™

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13th IEEE international symposium on parallel and distributed processing with applications

作者： Memeti, Suejb Pllana, Sabri Linnaeus Univ Dept Comp Sci S-35195 Vaxjo Sweden

ISBN: (纸本)9781467379526

Genetic information is increasing exponentially, doubling every 18 months. Analyzing this information within a reasonable amount of time requires parallel computing resources. While considerable research has addressed DNA analysis using GPUs, so far not much attention has been paid to the Intel Xeon Phi coprocessor. In this paper we present an algorithm for large-scale DNA analysis that exploits thread-level and the SIMD parallelism of the Intel Xeon Phi. We evaluate our approach for various numbers of cores and thread allocation affinities in the context of real-world DNA sequences of mouse, cat, dog, chicken, human and turkey. the experimental results on Intel Xeon Phi show speed-ups of up to 10x compared to a sequential implementation running on an Intel Xeon processor E5.

关键词： DNA Sequence Analysis DNA analysis genetic information parallel processing (COMPUTERS) acceleration core Coprocessors

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international Workshop on Intelligent Systems and Smart Home (WISH 2007)

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2007年 4743 LNCS卷 XI-XII页

作者： Yang, Laurence T. Guo, Minyi Hsu, Ching-Hsien Park, Jong Hyuk Wang, Cho-Li Pan, Gang

No abstract available

ISBN: (纸本)9783540747666

No abstract available

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Simulation-based performance analysis of a medical image-processing architecture

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11th international Workshop on Formal Methods for Industrial Critical Systems (FMICS 2006)/5th international Workshop on parallel and distributed Methods in Verification (PDMC

作者： Cuijpers, P. J. L. Fyukov, A. V. Tech Univ Eindhoven NL-5600 MB Eindhoven Netherlands Philips Res NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)9783540709510

In this paper, we show a simulation method for performance prediction of medical image processing chains, based on ***-time calculus of [9]. In particular, we focus on estimating the latency and throughput of a given image processing chain and its distribution over hardware resources. the architectural level of abstraction of the real-time calculus approach makes our method flexible, so that different design decisions can be studied using similar models. the choice for simulation rather than the usual algebraic analysis of real-time calculus equations, gives us the possibility to include a number of performance relevant implementation details in our models for which analytical estimates are not available.

关键词： Image processing

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Compression and Aggregation for Optimizing Information Transmission in distributed CNN 5

Compression and Aggregation for Optimizing Information Trans...

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5th international symposium on Computing and Networking (CANDAR)

作者： Mitani, Takamasa Fukuoka, Hisakazu Hiraga, Yuria Nakada, Takashi Nakashima, Yasuhiko Nara Inst Sci & Technol Grad Sch Informat Sci 8916-5 Takayama Cho Ikoma Nara 6300192 Japan

ISBN: (纸本)9781538620878

Modern deep learning has significantly improved the performance and has been used in a variety of applications. Due to the heavy processing cost, major platforms for deep learning have been migrated from commodity computers to the cloud where have huge amount of resources. However, the above situation leads to the slowdown of response time due to severe congestion of the network traffic. To alleviate the overconcentration of data traffic and power consumption, many researchers have paid attention to edge computing. We tackle with the parallel processing model using Deep Convolutional Neural Network (DCNN) employed on multiple devices, and the size reduction of network traffic among the devices. We propose a technique that compresses the intermediate data and aggregates common computation in AlexNet for video recognition. Our experiments demonstrate that Zip loss-less compression reduces the amount of data by up to 1/24, and HEVC lossy compression reduces the amount of data by 1/208 with only 3.5% degradation of the recognition accuracy. Moreover, aggregation of common calculation reduces the amount of computation for 30 DCNNs by 90%.

关键词： Convolution Neural Network Edge Computing Model parallel Video Compression Aggregation

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parallel algorithm of VLBI software correlator under multiprocessor environment - art. no. 678722

Parallel algorithm of VLBI software correlator under multipr...

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5th international symposium on Multispectral Image processing and Pattern Recognition

作者： Zheng Weimin Zhang Dong CAS Shanghai Astron Observ Shanghai 200030 Peoples R China

ISBN: (纸本)9780819469519

the correlator is the key signal processing equipment of a Very Lone Baseline Interferometry (VLBI) synthetic aperture telescope. It receives the mass data collected by the VLBI observatories and produces the visibility function of the target, which can be used to spacecraft position, baseline length measurement, synthesis imaging, and other scientific applications. VLBI data correlation is a task of data intensive and computation intensive. this paper presents the algorithms of two parallel software correlators under multiprocessor environments. A near real-time correlator for spacecraft tracking adopts the pipelining and thread-parallel technology, and runs on the SW (Symmetric Multiple Processor) servers. Another high speed prototype correlator using the mixed Pthreads and MPI (Massage Passing Interface) parallel algorithm is realized on a small Beowulf cluster platform. Both correlators have the characteristic of flexible structure, scalability, and with 10-station data correlating abilities.

关键词： VLBI software correlator parallel processing high performance computing cluster MPI Pthreads

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5th international symposium on High Performance Computing, ISHPC 2003

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5th international symposium on High Performance Computing, ISHPC 2003

ISBN: (纸本)3540203591

the proceedings contain 50 papers. the special focus in this conference is on Architecture, Software, applications and Implementations. the topics include: High performance computing trends and self adapting numerical software;overview of an adaptive multithreaded architecture;code and data transformations for improving shared cache performance on SMT processors;improving memory latency aware fetch policies for SMT processors;tolerating branch predictor latency on SMT;a simple low-energy instruction wakeup mechanism;field array compression in data caches for dynamically allocated recursive data structures;a generalized framework for auto-tuning software;evaluating heuristic scheduling algorithms for high performance parallel processing;pursuing laziness for efficient implementation of modern multithreaded languages;distribution-insensitive parallel external sorting on pc clusters;distributed genetic algorithm for inference of biological scale-free network structure;les of unstable combustion in a gas turbine combustor;grid computing supporting system on ITBL project;a visual resource integration environment for distributed applications on the ITBL system;development of remote visualization and collaborative visualization system in ITBL grid environment;performance of network intrusion detection cluster system;evaluation of high-speed VPN using CFD benchmark;virtual experiment platform for materials design;interconnection network system for clusters with wide-bandwidth and fault-tolerancy based on multiple links;a bypass-sensitive blocking-preventing scheduling technique for mesh-connected multicomputers;an optimal method for coordinated en-route web object caching and distributed location of shared resources and its application to the load sharing problem in heterogeneous distributed systems.

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SEMPLAR: High-performance remote parallel I/O over SRB

SEMPLAR: High-performance remote parallel I/O over SRB

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5th IEEE international symposium on Cluster Computing and the Grid (CCGrid 2005)

作者： Ali, N Lauria, M Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)0780390741

One of the challenges in high-performance computing is to provide users with reliable, remote data access in a distributed, heterogeneous environment. the increasing popularity of high-speed wide area networks and centralized data repositories lead to the possibility of direct high-speed access to remote data sets from within a parallel application. In this paper we describe SEMPLAR, a library for remote, parallel I/O that combines the standard programming interface of MPI-IO with the remote storage functionality of the SDSC Storage Resource Broker (SRB). SEMPLAR relies on parallel TCP streams to maximize the remote data throughput in a design that preserves the parallelism of the access all the way from the storage to the application. We have provided I/O performance resultsfor a high-performance computing work-load on three different clusters. On the NCSA TeraGrid cluster the ROMIO perf benchmark attained an aggregate read bandwidth of 291Mbps with 18 processors. the NAS btio benchmark achieved an aggregate write bandwidth of 74Mbps with 16 processors. the benchmark results are encouraging and show that SEMPLAR provides applications with scalable, high-bandwidth I/O across wide area networks.

关键词： parallel processing systems

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