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Morphological Similarity Based Livestock Prediction Using Machine Learning Technique

Morphological Similarity Based Livestock Prediction Using Ma...

引用

Recent Trends in computer Science and Technology (ICRTCST), International conference on

作者： C. S. Anita P. Shobha Rani Masthan Lakshmi Sahithi Maddali Monika J Rubeena Shaik Department Of CSE R.M.D. Engineering College Tamil Nadu India Full Stack Developer Virtusa Private Limited Chennai Tamil Nadu India

ISBN: (数字)9798350351378

ISBN: (纸本)9798350351385

In the current technological world, detection of stock market through various software systems is in practice. Predicting stock prices through recorded information of previous years, has enhanced the future prediction. Stock value information is viewed as a common place time in time series. In the existing system, a recurrent neural network(RNN), Long momentary memory (LMM) and gated rent units(GRU) are considered for regularizing the stock values that deals with sort of information. Considering the individual examination of stocks, according to the relativity between the existing stock and the whole market price, the proposed system analyzes the strategy behind. the proposed model considers clustering strategy for mining comfortable stocks which consolidate morphological comparison comparability distance MSD and K-means clustering. Further the system uses hierarchal temporal memory (HTM) model to which high course of data is initially depicted to learn then using the design among the comparative stocks and its information construction of inadequate stock values are normalized. In terms of prediction accuracy the proposed KMSD-LSTM model is improved in the prediction of price. LSTM model neglects the patterns that are not significantly related and remembers the pattern that makes a change in the prediction process.

关键词： Training Accuracy Transfer learning Time series analysis Predictive models User interfaces Agriculture

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Cost modeling for SDN/NFV based mobile 5G networks

Cost modeling for SDN/NFV based mobile 5G networks

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International conference on Ultra Modern Telecommunications and Workshops (ICUMT)

作者： Christos Bouras Panagiotis Ntarzanos Andreas Papazois Computer Engineering & Informatics Dept University of Patras Greece Computer Technology Institute & Press “Diophantus” Patras Greece

ISBN: (纸本)9781467388191

this paper presents a techno-economic analysis on the integration of new technologies in 5G mobile networks, in order to fulfil the requirements provided by ETSI organization. therefore “softwarization” of 5G networks is imperative and becomes a reality through new technologies, such as software Defined Networking (SDN), Network Function Virtualization (NFV) and Cloud Computing. In this context, this paper provides a cost model in order to estimate the Capital Expenditure (CAPEX), the Operational Expenditure (OPEX) and the Total Cost of Ownership (TCO) for the proposed architecture. Furthermore, the proposed techno-economic model is used in order to estimate the above-mentioned network costs for the proposed network architecture and these costs are compared with the corresponding costs of a traditional network architecture. the experimental results verify and even exceed the ambitious predictions for cost reduction, due to the integration of those state of the art technologies in next-generation architectures.

关键词： computer architecture Servers Mobile computing Cloud computing 5G mobile communication

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Rapid Prototyping of Digital Controllers for Microgrid Inverters

Rapid Prototyping of Digital Controllers for Microgrid Inver...

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Annual conference of the IEEE Industrial Electronics Society

作者： Simone Buso Tommaso Caldognetto DEI - Dept. of Information Engineering University of Padova

ISBN: (纸本)9781479902255

A rapid prototyping methodology for digital controllers is presented in this paper. Its main application is in the development, debugging and test of microgrid inverter controllers. To fulfill the application requirements, these systems are characterized by complex multilayer architectures, extending from PWM and current control loops up to global optimization and high level communication functions. the complexity and the wide variability of the different layer implementations make digital control mandatory. However, developing so complex digital controllers on conventional hardware platforms, like DSPs or even FPGAs, is not the most practical choice. the paper shows how multi-platform control devices, where software configurable DSP functions and programmable logic circuits are efficiently combined, represent the optimal solution for this field of application. Furthermore, the paper proposes hardware in the loop real time simulation as an effective means of developing and debugging complex hardware and software co-designed controllers. A case study is presented and used to illustrate the different design and test phases, from initial concept and numerical simulation to final experimental verification.

关键词： Microgrids Inverters Digital control Real time systems Inventors real-time systems MICRO-GRID digital controller Numerical controls rapid prototyping Hardware Platform HARDWARE IN thE LOOP computer hardware Current control

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A Deployment Scheme of YOLOv5 with Inference Optimizations Based on the Triton Inference Server

A Deployment Scheme of YOLOv5 with Inference Optimizations B...

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IEEE International conference on Cloud Computing and Big Data Analysis (ICCCBDA)

作者： Jiacong Fang Qiong Liu Jingzheng Li School of Software Engineering South China University of Technology Guangzhou China Zhuhai Unitech Power Technology Company Ltd

Object detection constitutes a large part of computer vision applications. You Only Look Once (YOLO) v5 is a salient object detection algorithm that provides high accuracy and real-time performance. this paper illustrates a deployment scheme of YOLOv5 with inference optimizations on Nvidia graphics cards using an open-source deep-learning deployment framework named Triton Inference Server. Moreover, we developed a non-maximum suppression (NMS) operator with dynamic-batch-size support in TensorRT to accelerate inference. the experimental results show that both throughput and latency are improved significantly through our deployment scheme.

关键词： Graphics Heuristic algorithms conferences Object detection throughput Real-time systems Inference algorithms

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A multi-agent control framework for co-adaptation in brain-computer interfaces 13

A multi-agent control framework for co-adaptation in brain-c...

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Annual conference on Neural Information Processing systems

作者： Josh Merel Roy Fox Tony Jebara Liam Paninski Department of Neurobiology and Behavior Columbia University New York NY 10027 School of Computer Science and Engineering Hebrew University Jerusalem 91904 Israel Department of Computer Science Columbia University New York NY 10027 Department of Statistics Columbia University New York NY 10027

ISBN: (纸本)9781632660244

In a closed-loop brain-computer interface (BCI), adaptive decoders are used to learn parameters suited to decoding the user's neural response. Feedback to the user provides information which permits the neural tuning to also adapt. We present an approach to model this process of co-adaptation between the encoding model of the neural signal and the decoding algorithm as a multi-agent formulation of the linear quadratic Gaussian (LQG) control problem. In simulation we characterize how decoding performance improves as the neural encoding and adaptive decoder optimize, qualitatively resembling experimentally demonstrated closed-loop improvement. We then propose a novel, modified decoder update rule which is aware of the fact that the encoder is also changing and show it can improve simulated co-adaptation dynamics. Our modeling approach offers promise for gaining insights into co-adaptation as well as improving user learning of BCI control in practical settings.

关键词： Brain-computer Interfaces decoders computer interfaces decoding algorithm linear quadratic Gaussian control ENCODER model codes DECODING simulating Awareness

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Asynchronous low power VLSI implementation of the International Data Encryption Algorithm

Asynchronous low power VLSI implementation of the Internatio...

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IEEE International conference on Electronics, Circuits and systems (ICECS)

作者： N. Sklavos O. Koufopavlou Electrical and Computer Engineering Department VLSI Design Laboratory University of Patras Patras Greece

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also designed. the VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercially available tools, the VHDL code was synthesized. After placing and routing, both designs were fabricated with 0.6 /spl mu/m CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V, the two chips were tested and evaluated, comparing them with the software implementation of the IDEA algorithm. this new approach proves efficiently the lower power consumption of the asynchronous implementation compared to the existing synchronous one. therefore the asynchronous chip performs efficiently in WEP (Wireless Encryption Protocols) and high speed networks.

关键词： Very large scale integration Cryptography Algorithm design and analysis CMOS technology Hardware design languages Routing Clocks Power supplies software testing System testing

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Research on High-Fidelity License Plates Generated Using Generative Adversarial Network (GAN) Technology for Vehicle Recognition systems 24

Research on High-Fidelity License Plates Generated Using Gen...

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13th International conference on software and computer Applications, ICSCA 2024

作者： Cheng, Yu-Huei Chen, Po-Yun Department Of Information And Communication Engineering Chaoyang University Of Technology Taiwan

ISBN: (纸本)9798400708329

In recent years, with the rapid advancement of artificial intelligence, deep learning techniques have seen extensive applications in various fields, including license plate recognition technology. However, deep learning-based license plate recognition still faces several challenges. For instance, it s often difficult to obtain a sufficiently diverse set of image data when collecting real-world data, and the quantity of data may not be enough to meet the training requirements of deep learning models. To address these challenges, this research proposes an approach based on Generative Adversarial Networks (GANs) to generate highly realistic license plate images. Instead of relying solely on traditional fixed cameras or on-site capture techniques to collect license plate datasets, this approach involves generating a diverse set of high-fidelity license plate images using randomization. this increases the diversity of the training dataset for deep learning, thereby improving the accuracy and generalization of license plate recognition technology. this paper utilizes both a real-world dataset of collected actual license plates and a high-fidelity synthetic dataset generated using GANs. these datasets are divided into eight groups, denoted as R_A, R_B, R_C, R_D, G_A, G_B, G_C, and G_D, each containing 6,000 to 12,000 license plate images. these datasets are used to train deep learning models based on the YOLOv5 architecture. the objective of the experiments is to compare the performance of the eight different license plate datasets after training, in order to validate whether the proposed high-fidelity synthetic dataset can replace traditional real-world license plate datasets. In the final experimental results, it is observed that the virtual license plates generated by the Generative Adversarial Networks can effectively replace real images captured by fixed cameras. the performance metrics for the eight groups are as follows: R_A: 82%, R_B: 85%, R_C: 93%, R_D: 95%, G_A:

关键词： Cameras

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Joint power and reduced spectral leakage-based resource allocation for D2D communications in 5G 15th

Joint power and reduced spectral leakage-based resource allo...

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15th International conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2015

作者： Mukherjee, Mithun Shu, Lei Zhang, Yan Zhou, Zhangbing Wang, Kun Guangdong Provincial Key Lab of Petrochemical Equipment Fault Diagnosis Guangdong University of Petrochemical Technology Guangdong525000 China Simula Research Laboratory University of Oslo Oslo Norway School of Information Engineering China University of Geosciences Beijing100083 China School of Internet of Things Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (纸本)9783319271392

this paper proposes a joint mode selection and resource block (RB) allocation for the direct device-to-device (D2D) communication underlying cellular network. Universal-filtered multi-carrier (UFMC) technique which is considered as a potential candidate for the future communication systems due to its robustness against inter\carrier interference (ICI), is introduced for D2D communication. In this paper, our goal is to design a network that selects the transmission mode between D2D and traditional cellular transmission mode. Unlike exist\ing work on the mode selection which focused on network performance to improve overall throughput and providing required quality-of-service (QoS) for cellular users (CUs), we study the interference from the other D2D links operating on the edge of the neighboring cells. D2D communications provide a reliable transmission near edge of the cells but is limited by interference from CUs as well as D2D pairs belong to edge of the neighboring cells. We present an approach in UFMC-based D2D scenario to reduce the spectral leakage to nearby RBs used for same or other D2D links. Further, we develop an optimization framework that aims to maximize signal-to-interference-and-noise ratio (SINR) and improves the overall throughput. © Springer International Publishing Switzerland 2015.

关键词： Resource allocation

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Implementation and Evaluation of Large Interconnection Routers for Future Many-core Networks on Chip

Implementation and Evaluation of Large Interconnection Route...

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IEEE International conference on High Performance Computing and Communications (HPCC)

作者： Amir H.M. Zaytoun Hossam A.H. Fahmy Khaled M.F. Elsayed Electronics and Communications Engineering Cairo University Egypt

As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to many-cores, the role of the interconnection communications becomes more critical. the number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the International Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented with m×n 2-D mesh topology connecting small size routers. this will represent the bottleneck to the communication latency for the increasing number of cores where the average number of hops the data have to pass will increase. In this paper, we propose an alternative NoC interconnecting scheme by using large routers interconnecting large number of cores in star topology. this interconnection scheme can be scaled up by using hierarchical-star or fat-tree topologies. We present the implementation and performance evaluation of three large router architectures and compare their efficiency to the small 5×5 router used in the mesh topology. We develop a simulating environment that resembles the real NoC conditions to test the routers throughput and average latency on different buffer sizes and under different traffic loads. We also synthesize them to estimate the area and power consumption. then, routers efficiencies are calculated with respect to the area and power consumption.

关键词： computer architecture Switches Microprocessors Topology Network topology Delay

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OpenSample: A Low-Latency, Sampling-Based Measurement Platform for Commodity SDN

OpenSample: A Low-Latency, Sampling-Based Measurement Platfo...

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International conference on Distributed Computing systems

作者： Junho Suh Ted Taekyoung Kwon Colin Dixon Wes Felter John Carter School of Computer Science and Engineering Seoul National University Seoul Korea Austin Research Lab IBM Research Austin TX

In this paper we propose, implement and evaluate OpenSample: a low-latency, sampling-based network measurement platform targeted at building faster control loops for software-defined networks. OpenSample leverages sFlow packet sampling to provide near-real-time measurements of both network load and individual flows. While OpenSample is useful in any context, it is particularly useful in an SDN environment where a network controller can quickly take action based on the data it provides. Using sampling for network monitoring allows OpenSample to have a 100 millisecond control loop rather than the 1-5 second control loop of prior polling-based approaches. We implement OpenSample in the Floodlight Open Flow controller and evaluate it both in simulation and on a test bed comprised of commodity switches. When used to inform traffic engineering, OpenSample provides up to a 150% throughput improvement over both static equal-cost multi-path routing and a polling-based solution with a one second control loop.

关键词： Monitoring Ports (computers) Control systems Radiation detectors Maximum likelihood estimation throughput Network topology

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