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Overview of Autonomous Driving Simulation Environment

Overview of Autonomous Driving Simulation Environment

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International conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS)

作者： Yunxiang Liu Yujie Pan Xinxin Yuan Yuntao Zhao School of Computer Information and Engineering Shanghai Institute Of Technology Shanghai China R&D Department Shanghai Waylancer Automotive Technology Co. Ltd Shanghai China

the goal of many companies is to provide auto drive system that meet SAE Level 5. Due to the much more complex software running on these systems than typical high-end cars today, a thorough testing strategy is required. Simulation test is an essential part of the development process of autonomous vehicle. At present, there are many automatic driving simulation platforms. this papper summarizes the development status and existing problems of autonomous driving simulation platforms by organizing them from aspects such as simulation hierarchy, simulation content, and usage, and proposes the development trend of autonomous driving simulation platforms.

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A novel 100 watt High Intensity Focused Ultrasound driving system

A novel 100 watt High Intensity Focused Ultrasound driving s...

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Annual International conference of the IEEE engineering in Medicine and Biology Society (EMBC)

作者： David A. Steines Kie-Bum Eom thomas Manuccia Vesna Zderic Department of Electrical and Computer Engineering George Washington University Washington D.C. DC USA

Ultrasound B-Mode imaging systems are often used to image tissues to which High Intensity Focused Ultrasound (HIFU) is being applied. Since HIFU operates at frequencies in the same range as a B-mode imager, the two technologies interfere when they are simultaneously applied to the patient. this causes the imaging window to “whiteout” and obscure the target region, thus defeating the purpose of using the ultrasonic imager in the first place. the system in this paper controls the interference window by pulsing the HIFU at a frame rate synchronized to the ultrasonic imager. the frame rate is either approximated by using an on-board oscillator, or it is captured from stray electromagnetic waves received from the ultrasound transducer. the system is capable of delivering 100 W of peak electrical output power to a HIFU transducer. It is controlled by a custom software application, and synchronizes with B-Mode imaging systems with frame rates from 10–100 Hz. An on-board Direct Digital Synthesizer generates HIFU RF from 1–5MHz. the complete system provides precision positioning of the interference window in a small and portable desktop package.

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An improved Non-Isolated Multiple-Input buck dc-dc converter

An improved Non-Isolated Multiple-Input buck dc-dc converter

引用

Power Electronic and Drive systems and Technologies conference (PEDSTC)

作者： Kazem Varesi Seyed Hossein Hosseini Mehran Sabahi Ebrahim Babaei Naser Vosoughi Faculty of Electrical and Computer Engineering University of Tabriz Tabriz Iran

ISBN: (纸本)9781509026951

In this paper, an improved Non-Isolated bidirectional Multiple-Input (MI) Buck dc-dc converter has been proposed. In the proposed topology, the input sources can simultaneously/independently transfer energy to the load. the applied energy storage system -battery- not only realizes the bidirectional power flow (even when none storable input sources like Fuel Cells are utilized), but also can absorb the excess energy produced by input sources. Simple structure and reduced number of components (switches, inductors, capacitors and current sensors) are the main advantages of the proposed topology. Different operational modes and design consideration of proposed converter have been investigated. To confirm the validity of proposed converter, the two-input version has been modeled and simulated in PSCAD/EMTDC software and implemented experimentally. Obtained results validate the suitable performance of proposed topology.

关键词： Switches Video recording Integrated circuits Topology TV 5G mobile communication Inductance

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Constructing a Mobility and Acceleration Computing Platform with NVIDIA Jetson TK1

Constructing a Mobility and Acceleration Computing Platform ...

引用

IEEE International Symposium on Cyberspace Safety and Security

作者： Min Su Jianjun Tan Chun-Yuan Lin Jin Ye Chung-Hung Wang Che-Lun Hung College of Life Science and Bioengineering Beijing University of Technology Department of Computer Science and Information Engineering Chang Gung University Department of Computer Science and Communication Engineering Providence University

ISBN: (纸本)9781479989386

Current high-end graphics processing units (GPUs), which contain up to thousand cores per-chip, are widely used in the high performance computing community. However, in the past, the cost and power consumption of constructing a high performance platform with graphics cards, such as Tesla and Fermi series, are high. Moreover, these graphics cards all installed in personal computers or servers, and then the immediate and mobility requirements can not be provided by this platform. NVIDIA Jetson TK1 (Tegra K1) is a full-featured platform for embedded applications and it contains 192 CUDA Cores (Kepler CPU). Due to its low cost, low power consumption and high applicability, NVIDIA Jetson TK1 has become a new research direction. In this paper, we construct a mobility and acceleration computing platform with NVIDIA Jetson TK1. Besides, two tools, ClustalWtk and MCCtk are designed based on NVIDIA Jetson TK1. these tools both can achieve 3 and 4 times speedup ratios on single NVIDIA Jetson TK1 by comparing with their CPU versions on Intel XEON E5-2650 CPU and ARM Cortex-A15 CPU, respectively. Moreover, the cost-performance ratio by NVIDIA Jetson TK1 is higher than that by NVIDIA Tesla K20m. In addition, the user friendly interfaces are also provided by these two tools, respectively.

关键词： NVIDIA Jetson TK1 CUDA Mutliple Sequence Alginment Compound Comparison Parallel Processing

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Design and application of intelligent edge terminals

Design and application of intelligent edge terminals

引用

Electronic Information engineering and computer Communication (EIECC), International conference on

作者： Yan Liu Enguo Zhu Metering Department China Electric Power Research Institute Beijing China

ISBN: (数字)9798331534622

ISBN: (纸本)9798331534639

With the continuous development of 5G technology and the large-scale connection of new energy, traditional power terminals can no longer meet new business needs such as real-time energy and refined load management of electricity users. therefore, based on the business needs of major scenarios such as smart home appliances, smart buildings, and smart parks, this paper carries out the development of intelligent edge terminals (IEU), realizing high-frequency collection of massive energy consumption data based on 5G communication technology. It introduces D2D technology to build communication links between terminals, which further enhances data transmission rate. At the same time, it realizes load identification and load prediction based on the edge computing capabilities. It also realizes real-time regulation and management of load resources to achieve intelligent monitoring of electrical equipment.

关键词： Home appliances Smart buildings 5G mobile communication Smart homes Real-time systems Hardware software Regulation Business Edge computing

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Experimental Analysis of SMP Scalability in the Presence of Coherence Traffic and Snoop Filtering

Experimental Analysis of SMP Scalability in the Presence of ...

引用

IEEE International conference on High Performance Computing and Communications (HPCC)

作者： Mayez A. Al-Mouhamed Khaled A. Daud Department of Computer Engineering King Fahd University of Petroleum &Minerals Dhahran K. S. A

Commodity multi-core SMPs may generate an enormous amount of coherency traffic. However, the impact of coherence traffic and snoop filtering on parallel program scalability has not attracted sufficient attention. We experimentally analyze the shared data access patterns of four typical applications having different memory layout. An OpenMp optimized execution model is derived for each application with emphasis on data dependencies and implied coherence messages. Using an 8-core SMP we present the obtained speedups versus change in the number of cores and problem scale. A discussion of potential limitation on scalability due to the application or SMP is presented. To assess the coherence behavior and its impact on scalability of parallel programs, a synthetic benchmark which alternates the data block ownership among two cores of the same or different processors is presented. It is found that coherence overheads including snoop filtering are responsible of significant limitation on parallel program scalability. For 8-core SMPs, speedup can be reduced by factors of 2.5 and 5 for row-major and column-major access patterns as compared to the use of private data, respectively. A truly parallel coherence protocol implementation is needed to provide truly scalable shared-memory model.

关键词： Coherence Mathematical model Program processors Computational modeling Scalability Arrays Jacobian matrices

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Research on the Application of Artificial Intelligence in Cybersecurity: Integrating Advanced Technologies to Improve threat Detection and Response

Research on the Application of Artificial Intelligence in Cy...

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Global conference for Advancement in Technology (GCAT)

作者： T.S.Balaji R.Nadanasabai Rajesh Jagadeesan Ravikumar S.Sharanyaa R.Meenal Nandigam Poornima Deepthi Department of Electronics and Communication Engineering Faculty of Engineering and Technology SRM Institute of Science and Technology Chennai Department of MBA St.Josephs College of Engineering Chennai Software Engineering Senior Advisor Evernorth Health Services Chattanooga TN Department of Information Technology Panimalar Engineering College Chennai Tamil Nadu India Department of Electrical and Electronics Engineering V.S.B Engineering College India Department of ECE MLR Institute of Technology Hyderabad

ISBN: (数字)9798350376685

ISBN: (纸本)9798350376692

In the current age of digital change, the field of cybersecurity is faced with progressively advanced and enduring dangers. Conventional security measures are finding it difficult to keep up with the fast-changing nature of cyber threats. Artificial intelligence (AI) offers a significant chance to enhance threat detection and response systems by leveraging its sophisticated data processing and pattern recognition abilities. this study explores the incorporation of artificial intelligence (AI) technology in the field of cybersecurity, specifically aiming to improve the effectiveness of systems that identify and respond to threats. the paper commences by examining the present difficulties encountered by cybersecurity experts, which encompass the large number and diverse range of potential threat vectors, the covert and flexible nature of contemporary malware, and the limitations imposed by resource constraints on the efficacy of human-driven analysis. the text explores the current cutting-edge AI strategies used to tackle these difficulties, including anomaly identification through machine learning algorithms, predictive analysis using deep learning models, and threat intelligence collecting through natural language processing. the research also examines the distinct factors of AI in the cybersecurity field, such as the requirement for immediate decision-making, the significance of comprehending the model, and the possibility of hostile attacks on AI systems. this study seeks to analyse current literature and emerging trends to gain a deep understanding of how artificial intelligence (AI) can enhance cybersecurity. Additionally, it aims to identify the obstacles and deficiencies that must be overcome to effectively incorporate AI technologies into this crucial domain. To summarise, the research highlights the considerable capacity of AI to transform cybersecurity practices, providing a way to develop more robust and flexible defence methods against the numerous danger

关键词： Deep learning Ethics Machine learning algorithms Transforms Semisupervised learning threat assessment Vectors Safety Artificial intelligence computer security

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Study on Multi-Vehicle Scheduling Problem

Study on Multi-Vehicle Scheduling Problem

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International conference on computer Supported Cooperative Work in Design

作者： Jian Wang Wei Yang Liusheng Huang Boqiang Li School of Computer Science and Technology University of Science and Technology of China Hefei P.R. China School of Software Engineering University of Science and Technology of China Hefei P.R. China

ISBN: (纸本)9781728165974;9781728165981

In the age of 5G, everything is connected. the departure site, destination site, departure time and other information of all vehicles on the road can be known by the unified dispatching center. therefore, on this basis, the vehicle routing model in the traffic network is established. In the scheduling model, the real world vehicle driving situation is simulated by setting the road vehicle scheduling strategy and the intersection passing strategy. By considering the deadlock state, the problem of priority of vehicles passing through the intersection is solved. Considering the congestion in the road and the frequent use of the road in the network center, the whole road grid is layered. the heuristic algorithm with path congestion is used to calculate the route selection of vehicles in real time. the experimental results show that the total scheduling time and waiting time can be effectively reduced when the route scale and vehicle scale are large.

关键词： Processor scheduling Roads Heuristic algorithms Road vehicles System recovery Routing Real-time systems

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Improving Coding Performance and Energy Efficiency of Erasure Coding Process for Storage systems - A Parallel and Scalable Approach

Improving Coding Performance and Energy Efficiency of Erasur...

引用

IEEE International conference on Cloud Computing, CLOUD

作者： Hsing-Bung Chen Song Fu HPC-5 Group Los Alamos National Lab Los Alamos New Mexico USA Department of Computer Science and Engineering University of North Texas Texas Denton

Erasure code based object storage systems are becoming popular choices for archive storage systems due to cost-effective storage space saving schemes and higher fault-resilience capabilities. Both erasure code encoding and decoding procedures involve heavy array, matrix, and table-lookup compute intensive operations. With today's advanced CPU design technologies such as multi-core, many-core, and streaming SIMD instruction sets we can effectively and efficiently adapt the erasure code technology in cloud storage systems and apply it to handle very large-scale date sets. Current solutions of the erasure coding process are based on single process approach which is not capable of processing very large data sets efficient and effectively. To prevent the bottleneck of a single process erasure encoding process, we utilize the task parallelism property from a multicore computing system and improve erasure coding process with parallel processing capability. We have leveraged open source erasure coding software and implemented a concurrent and parallel erasure coding software, called parEC. the proposed parEC process is realized through MPI run time parallel I/O environment and then data placement process is applied to distribute encoded data blocks to their destination storage devices. In this paper, we present the software architecture of parEC. We conduct various performance testing cases on parEC's software components. We present our early experience of using parEC, and address parEC's current status and future development works.

关键词： Encoding software Multicore processing Testing Parallel processing Bandwidth Parallel programming

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Temperature, Voltage, and Aging Effects in Ring Oscillator Physical Unclonable Function

Temperature, Voltage, and Aging Effects in Ring Oscillator P...

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IEEE International conference on High Performance Computing and Communications (HPCC)

作者： Muslim Mustapa Mohammed Niamat Department University of Toledo Electrical Engineering and Computer Science Toledo OH USA

ISBN: (纸本)9781479989386

Physical unclonable functions (PUFs) are security features that are based on process variations that occur during silicon chip fabrication. As PUFs are dependent on process variations, they need to be robust against reversible and irreversible temporal variabilities. In this paper, we present experimental results showing temporal variability in 4, 5, and 7-stage ring oscillator PUFs (ROPUFs). the reversible temporal variabilities are studied based on voltage and temperature variations, and the irreversible temporal variabilities are studied based on accelerated aging. Our results show that ROPUFs are sensitive to temperature and voltage variations regardless of the number of RO stages used. It is also observed that the aging, temperature, and voltage variation effects are observed to be uniformly distributed throughout the chip. this is evidenced by noting uniform changes in the RO frequency. Our results also show that most of the bit flips occur when the frequency difference in the RO pairs is low. this leads us to the conclusion that RO comparison pairs that pass high frequency threshold should be filtered to reduce temporal variabilities effect on the ROPUF. the experimental results also show that the 3-stage ROPUF has the lowest percentage of bit flip occurrences and the highest number of RO comparison pairs that pass high frequency threshold.

关键词： Aging Field programmable gate arrays Logic gates Silicon Security Ring oscillators Temperature sensors

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