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Time-frequency analysis using sidelobe apodization

Time-frequency analysis using sidelobe apodization

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conference on advanced signal processing algorithms, architectures, and implementations XI

作者： thomas, G Univ Manitoba Dept Elect & Comp Engn Winnipeg MB R3T 5V6 Canada

ISBN: (纸本)0819441880

Time-frequency techniques have been successfully used in the analysis of non-stationary signals. Several approaches have been proposed that address concerns such as Time-Frequency (TF) resolution and the elimination of cross-terms. In this work, a TF technique based on the use of Spatially Variant Apodization (SVA) is introduced that focuses on the detection of non-stationary signals that consists of several components that have different amplitudes. the SVA approach is applied to the Short-Time Fourier Transform (STFT) to detect small intensity components that are buried in high sidelobes of other components. Resolution using the SVA is better than the resolution obtained using the STFT with non-rectangular windows. Synthesis can be performed using the overlap-add method. Because of the implementation of the SVA, the modified STFT using sidelobe apodization can have good resolution, detect small intensity components, and show no cross terms in the TF plane, given that stationarity can be assumed using an appropriate window length in the STFT.

关键词： sidelobe apodization time-frequency analysis resolution cross-terms overlap-add reconstruction

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Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

Efficient implementations of pipelined CORDIC based IIR digi...

引用

spie conference on advanced signal processing algorithms, architectures, and implementations VIII

作者： Ma, J Parhi, KK Hekstra, GJ Deprettere, EF Univ Minnesota Dept ECE Minneapolis MN 55455 USA

ISBN: (纸本)0819429163

CORDIC based IIR digital filters are orthogonal filters whose internal computations consist of orthogonal transformations. these filters possess desirable properties for VLSI implementations such as regularity, local connection, low sensitivity to finite word-length implementation, and elimination of limit cycles. Recently, fine-grain pipelined CORDIC based IIR digital filter architectures which can perform the filtering operations at arbitrarily high sample rates at the cost of linear increase in hardware complexity have been developed. these pipelined architectures consist of only Givens rotations and a few additions which can be mapped onto CORDIC arithmetic based processors. However, in practical applications, implementations of Givens rotations using traditional CORDIC arithmetic are quite expensive. For example, for 16 bit accuracy, using floating point data format with 16 bit mantissa and 5 bit exponent, it will require approximately 20 pairs of shift-add operations for one Givens rotation. In this paper, we propose an efficient implementation of pipelined CORDIC based IIR digital filters based on fast orthonormal mu-rotations. Using this method, the Givens rotations are approximated by angles corresponding to orthonormal mu-rotations, which are based on the idea of CORDIC and can perform rotation with minimal number of shift-add operations. We present various methods of construction for such orthonormal mu-rotations. A significant reduction (over 76%) of the number of required shift-add operations is achieved. All types of fast rotations can be implemented as a cascade of only four basic types of shift-add stages. these stages can be executed on a modified floating-point CORDIC architecture, making the pipelined filter highly suitable for VLSI implementations.

关键词： orthogonal IIR digital filters pipelining approximate rotations orthonormal mu-rotations CORDIC architecture

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RECENT ADVANCES IN NONSTATIONARY signal ANALYSIS - TIME-VARYING HIGHER-ORDER SPECTRA AND MULTILINEAR TIME-FREQUENCY signal ANALYSIS 4

RECENT ADVANCES IN NONSTATIONARY SIGNAL ANALYSIS - TIME-VARY...

引用

4th CONF ON advanced signal processing algorithms, architectures, and implementations

作者： BOASHASH, B Queensland Univ. of Technology (Australia)

ISBN: (纸本)0819412767

this paper is written to provide both a historical review of past work and an overview of recent advances in time-frequency signal analysis and time-varying higher-order spectra. the paper is organized as follows: Section 1 discusses the need for time-frequency signal analysis (TFSA), as opposed to either time or frequency analysis. Section 2 covers the many faceted developments which occurred in TFSA in the 1980s and early 1990s. It covers bilinear or energetic time-frequency distributions (TFDs). Section 3 deals with a generalization of bilinear TFDs to multilinear Polynomial TFDs and their relationship to time-varying higher order spectra (TVHOS). Section 4 provides a coverage of the Wigner-Ville trispectrum, which is a particular TVHOS, used for analyzing signals affected by Gaussian multiplicative noise. Section 5 is devoted to conclusions.

关键词： Frequency modulation Fermium Interference (communication) Fourier transforms signal to noise ratio Time-frequency analysis signal analysis signal processing signal analyzers Nonlinear optics

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High-performance fine-grained pipelined LMS algorithm in virtex FPGA

High-performance fine-grained pipelined LMS algorithm in vir...

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conference on advanced signal processing algorithms, architectures, and implementations X

作者： Ting, LK Woods, RF Cowan, CFN Cork, P Sprigings, C Queens Univ Belfast Dept Elect & Elect Engn Belfast BT9 5AH Antrim North Ireland

ISBN: (纸本)0819437611

this paper presents the design, implementation, and verification of fine-grained pipelined Least-Mean-Square (LMS) adaptive Finite-Impulse-Response (FIR) filters in Virtex FPGA technology. the paper focuses on the impact of introducing pipelining into the LMS filter. Whilst pipelining provides a speed increase, the additional effect is to introduce delay into the error feedback loop which degrades performance. this effect is overcome through the use of look-ahead and delayed LMS based algorithms. In addition, the paper shows that FPGA technology, such as the Virtex FPGA is an ideal platform for this implementation, as the costs of pipelining are offset by the availability of high levels of flipflops within the FPGA architecture. A pipelined momentum LMS algorithm is identified, which is considered to offer a better convergence behaviour and tracking capability than the pipelined LMS algorithm. Detailed performance results including area and timing figures based on actual FPGA layout are given.

关键词： adaptive filters pipelined LMS algorithm momentum LMS virtex FPGA implementation

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Pairing in cryptography: an arithmetic point of view

Pairing in cryptography: an arithmetic point of view

引用

conference on advanced signal processing algorithms, architectures, and implementations XVII

作者： Bajard, J. C. El Mrabet, N. Univ Montpellier 2 CNRS ARITH LIRMM F-34095 Montpellier 5 France

ISBN: (纸本)9780819468451

the pairing is a mathematical notion wich appeared in cryptography during the 80'. At the beginning, it was used to build attacks on cryptosystems, transferring the discrete logarithm problem on elliptic curves, to a discrete logarithm problem on finite fields, the first was the MOV36 attack in 1993. Now, pairings are used to construct some cryptographic protocols: Diffie Hellman tripartite, identity based encryption, or short signature. the main two pairings usually used are the Tate and Weil pairings. they use distortions and rationnal functions, and their complexities depends of the curve and the field involved. this study deals with two particular papers: one due to N. Koblitz and A. Menezes(27) published in 2005, and a second one written by R Granger, D. Page and N. Smart(24) in 2006. these two papers compare Tate and Weil pairings, but they differ in their conclusions. We consider the different arithmetic tricks used, trying to precise each point, in a way to avoid any ambiguity. thus, the arithmetics proposed take into account the features of the fields and the curves used. We clarify the complexity of the possible implementations. We compare the different approaches, in order to clarify the conclusions of the previous papers.

关键词： pairing arithmetic operators

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Systolic Digital IIR Filter architectures for Real Time signal processing Applications 5

Systolic Digital IIR Filter Architectures for Real Time Sign...

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5th IEEE International conference for Emerging Technology, INCET 2024

作者： Penumutchi, Bujjibabu Tatikonda, Gayatri Surampalem India Surampalem India

ISBN: (纸本)9798350361155

Digital signal processing (DSP) is a critical area of research within Very Large-Scale Integration (VLSI) due to its vital role in various applications such as telecommunications, multimedia, radar, and medical imaging. DSP is essential for achieving real-time performance, low power consumption, and optimized hardware implementations. As VLSI technologies advance to support emerging fields like AI, IoT, and edge computing, DSP remains essential, driving innovations in algorithms and architectures to meet the demands of these rapidly advancing technologies. Here we are using different architectures for reducing usage of power, delay and PDP and also to find efficiency Quality Metrics is provided. © 2024 IEEE.

关键词： Digital signal processing

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Some improvement on RNS montgomery modular multiplication

Some improvement on RNS montgomery modular multiplication

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conference on advanced signal processing algorithms, architectures, and implementations X

作者： Bajard, JC Didier, LS Kornerup, P Rico, F LIRMM F-34392 Montpellier 5 France

ISBN: (纸本)0819437611

In Residue Number Systems (RNS), an integer X is represented by its residues {x(0),...,x(n-1)} modulo a base of relatively prime numbers {m(0),...,m(n-1)}. thus a large number can be represented as a set of small integers. Addition and multiplication can be easily parallelized, there is no carry propagation. the time is reduced to the evaluation of these operations with small numbers. this representation is useful in cryptography and digital signal processing. Furthermore, in these two domains, modular multiplication (A x B mod N) is frequently used. So, in 1998, we have presented in IEEE journal of transactions on computers,(20) a new modular multiplication algorithm in RNS. this algorithm is based on the Montgomery algorithm: using the associated Mixed Radix representation;for the weighted digits. It was the first algorithm of this type. In this paper, we present two remarks. First, if we develop the different expressions due to the algorithm, we obtain some mathematical simplifications that allow us to suppress some Mixed Radix occurrence in the basic iteration simply with a new initialization of our variables. thus, in this new version, the complexity of each basic iteration, becomes equivalent to two products of small integers instead of three. the second remark is that, most of the time, modular multiplications are done with the same modulo N. We can precompute some values and reduce the complexity of each basic iteration to one multiplication of two small integers. thus, the basic iteration is three time faster and the global computation, due to the initialization, is 8/5 time faster than the original version. Sometime after the last basic iteration a Mixed Radix conversion can be needed. Classical parallel methods are linear. We propose an logarithmic parallel algorithm for this translation from RNS to Mixed Radix. Far this, we use a result that comes from an RNS division algorithm, we published in Journal of VLSI signal processing systems 1998.(3) We obtain

关键词： modular multiplication montgomery residue number system mixed radix

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Efficient realization of the M-D nonrecursive filters: From sequential implementation to mapping on systolic array processors

Efficient realization of the M-D nonrecursive filters: From ...

引用

5th IEEE International conference on Electronics, Circuits and Systems, ICECS 1998

作者： Burian, Adrian Rusu, Corneliu Kuosmanen, Pauli Signal Processing Laboratory Tampere University of Technology P.O. Box 553 TampereFIN-33101 Finland

ISBN: (纸本)0780350081

this paper presents algorithms and architectures for implementing from 1-D to multidimensional M-D digital nonrecursive filters. these architectures are very regular and support single chip implementation in VLSI, as well as multiple chip implementations. the proposed systolic arrays, used in implementation of these algorithms, are optimal with respect to time. In a systolic implementation the highest degree of parallel processing and thus performance is achieved. But with this implementation the highest number of gates and thus complexity is obtained. As a compromise, we propose and analyse simpler systolic system for realtime nonrecursive filtering. © 1998 IEEE.

关键词： Systolic arrays

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NEURAL-NETWORK IMPLEMENTATION OF MAthEMATICAL MORPHOLOGY OPERATION 5

NEURAL-NETWORK IMPLEMENTATION OF MATHEMATICAL MORPHOLOGY OPE...

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5th International conference on Applications of Artificial Neural Networks

作者： TAO, P SHANGHAI JIAO TONG UNIV INST IMAGE PROCSHANGHAI 200030PEOPLES R CHINA

ISBN: (纸本)0819415472

this paper proposes a feedforward neural network structure to realize the mathematical morphology operations (MMO), namely: HMT (Hit and Miss Transformation), dilation, erosion, opening, closing, and the union and intersection (for multistructuring elements and multioperators) of them. Different kinds of operations can be implemented by assigning the weights, the threshold values and the architecture of the network according to the operation itself to be implemented. A general expression relating the weight value, threshold value to the configuration of the structuring element for different operations is derived, the assigning of the values becomes merely straight-forward training procedure of the proposed network. Also, it is proved that with a single hidden layer, all the MMO can be implemented by the ANN. the most interesting aspect of the method proposed is the reduction of on-line operation steps, which for conventional MMO algorithm consist of a series of operations processed consecutively. As a extension of the method, Boolean function implementations of the operations are also proposed, in which, the concept of collection of basic `And' structuring elements is presented. We prove that all MMO sequence can be implemented by a 2-layer logic gate array (or 3 layers in the sense of node levels).

关键词： Berkelium Logic devices Mathematical morphology Neural networks Binary data Network architectures signal processing Transform theory Logic Parallel processing

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signal processing for smart cards

Signal processing for smart cards

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5th conference on Security and Watermarking of Multimedia Contents

作者： Quisquater, JJ Catholic Univ Louvain Crypto Grp B-1348 Louvain Belgium

ISBN: (纸本)0819448206

In 1998, Paul Kocher showed that when a smart card computes cryptographic algorithms, for signatures or encryption, its consumption or its radiations leak information [1]. the keys or the secrets hidden in the card can then be recovered using a differential measurement based on the intercorrelation function. A lot of silicon manufacturers use desynchronisation countermeasures to defeat power analysis. In this article we detail a new resynchronisation technic. this method can be used to facilitate the use of a neural network to do the code recognition. It becomes possible to reverse engineer a software code automatically. Using data and clock separation methods, we show how to optimize the synchronization using signal processing. then we compare these methods with watermarking methods for 1D and 2D signal. the very last watermarking detection improvements can be applied to signal processing for smart cards with very few modifications. Bayesian processing is one of the best ways to do Differential Power Analysis, and it is possible to extract a PIN code from a smart card in very few samples. So this article shows the need to continue to set up effective countermeasures for cryptographic processors. Although the idea to use advanced signal processing operators has been commonly known for a long time, no publication explains that results can be obtained. the main idea of differential measurement is to use the cross-correlation of two random variables and to repeat consumption measurements on the processor to be analyzed. We use two processors clocked at the same external frequency and computing the same data. the applications of our design are numerous. Two measurements provide the inputs of a central operator. With the most accurate operator we can improve the signal noise ratio, re-synchronize the acquisition clock with the internal one, or remove jitter. the analysis based on consumption or electromagnetic measurements can be improved using our structure. At first si

关键词： signal to noise ratio Interference (communication) Clocks signal processing Electromagnetism Convolution Sensors Statistical analysis Fourier transforms Digital watermarking

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